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« on: June 18, 2020, 10:06:33 AM »
Hi,
and once again thanks for the replies.
Darkjezter: you make a very good point about the display list swap process. My idea would work if the chip has 2 internal areas of memory and a pointer is deciding which area I can write into while the other area is being displayed, but, if I failed to write my subroutine into high memory each time I wanted to swap then the display process would go wrong!!
BRT Community: thanks for the link to SampleApp, I will check through it for further inspiration. Also thanks for the details about the rame rates etc. Is there a simple way to know how long it takes to process a Display List when it is being displayed to be sure that it is not overrunning ? Perhaps in any new chips we could have a STATUS register that could include a Display Overrun flag ? Perhaps there already is one and I've just never found it...
I have changed my CPU process a little so that I now build a "table" of CoProcessor commands in memory and so now the problem of how to determine the offset address to the subroutine becomes a 'C' coding problem. It would be nice to be able to create a "label" at the point in the table where the subroutine is and refer to it by name as the address for the CALL. Sadly 'C' does not allow you to put lables in arrays, only in code functions.
Anyway. I have learned a great deal more about the EVE chip through this, can't wait for the next, bigger version to become available!!
PhilipJ