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Messages - marcolando

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1
Hi, thank you for the reply.
I think I found the issue: I was taking account of the FIFO roll over only when I was updating REG_CMD_WRITE at the end of the display list, but not when I was sending the memory address at the beginning of each data bursts.
After doing the correction now it seems to work perfectly.
Thank you for the support, going deep in your suggest to report the FIFO counter handling let me understood the problem!

Regards,
Marco.

2
Hello everybody,
I'm using a FT801 to drive a TFT display for show a menu interface; I send the display list through the Co-processor's FIFO.
Here is my problem: since the FT801 start and has been configured, the mcu sends a single display list, composed of 6 data bursts, for a total of 262byte (3bytes for the FIFO writing address at each burst + a total of 244bytes of payload/commands).
Bursts are repeated when the interface needs to change some parameters, button colors for example.
The FIFO memory address pointer starts from 0x0000 and, after the first complete data set the pointer is 0x00F4, then 0x01E8 after the second one and so on until the FIFO reaches the end and wraps newly from the beginning: .... 0x0F40 -> 0x0034 -> ...
Everything works fine until the FIFO wraps 0x0000 the 4th time (... 0x0FDC -> 0x00D0) at wich the display starts showing the FTDI logo!
Have you got any idea on this "strange" beahaviour of the FT801? What kind of test you suggest should I do in order to find the problem in my code?

Thank you very much in advance for the support,
Regards.

Marco.

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