BRT Community

General Category => Discussion - EVE => Topic started by: Cyrilou on February 08, 2021, 01:28:03 PM

Title: ESD 4.10 display instabilities
Post by: Cyrilou on February 08, 2021, 01:28:03 PM

Hi,

I 've made a screen with ontly 3 labels rendered in the normal loop of ESD4.10 exported eclipse project on a renesas synergy MCU.
I've enabled  _DEBUG preprocessor.
It can display 10 minutes without errors and suddenly
I encounter many display glitches and hanging randomly:
- "illegal option in cmd_text"
- bad characters
- screen becomes black but program runs normally in background and i'm unable to unlock it since there is no error detected. I must unplug power to unlock it.

It's like BT815 was in a normal state but not the screen...
Modify SPI bitrate changes nothing.

Do you know what the cause?

Title: Re: ESD 4.10 display instabilities
Post by: Cyrilou on February 09, 2021, 02:01:30 PM

When screen is black (or white, it depends) coprocessor fifo space is not released, it makes a resetcoprocessor, after cmdb_space =4092, I make 2 writes and cmdb_space=4084 but is not released and so on!
I think coprocessor is locked. How to unlock it without switch off/on power?

Title: Re: ESD 4.10 display instabilities
Post by: BRT Community on February 10, 2021, 02:50:16 PM

Hello,

Thank you for your question.

Please see section 5.7 of the programmers guide:
https://brtchip.com/wp-content/uploads/Support/Documentation/Programming_Guides/ICs/EVE/BRT_AN_033_BT81X_Series_Programming_Guide.pdf (https://brtchip.com/wp-content/uploads/Support/Documentation/Programming_Guides/ICs/EVE/BRT_AN_033_BT81X_Series_Programming_Guide.pdf)

This covers how to read co-processor faults, which would help use determine if this is the cause of the screen issues you are seeing. It also includes the recommended recovery procedure  for when a fault is detected.

Best Regards,
BRT Community

Title: Re: ESD 4.10 display instabilities
Post by: Cyrilou on February 15, 2021, 08:34:39 AM

Recovery procedure are already handled by ESD exclipse export. The main problem here is that coprocessor fifo is in an instable state even if we use recovery procedure or reset  the chip (powercycle function) without unplug power. We must add serial and pull up resistors  to adapt impedance  of SPI bus lines like in Ft800 datasheet suggest.

I think there is a case where we can lock FIFO memory and today there is no way to unlock it even in datasheet. You must reproduce this problem and correct it.

Title: Re: ESD 4.10 display instabilities
Post by: BRT Community on February 15, 2021, 01:38:20 PM

Hello

Would it be possible for you to share your project with us so we can investigate this issue further?
Can you also give me details on your hardware setup, i.e which MCU are you using?

Best Regards,
BRT Community

Title: Re: ESD 4.10 display instabilities
Post by: Cyrilou on February 17, 2021, 10:49:02 AM

No need to give you the project.
I think there is a hardware problem that cause a software problem on coprocessor fifo.

If I make a contact on SCK of spi with my oscilloscope probe I can lock fifo easily. Probe has an effect of antenna that degrades the SCK signal.

On the other hand if I wires screen without the ribbon cable FFC (standard wires)I have no problems.

Title: Re: ESD 4.10 display instabilities
Post by: BRT Community on February 17, 2021, 02:54:46 PM

Hello,

Thank you for the update.
Yes it is possible that a slight hardware issue with the SPI signals may be causing the issue with the co-processor.
Please let us know if you have any further issues.

Best Regards,
BRT Community

Title: Re: ESD 4.10 display instabilities
Post by: Cyrilou on February 24, 2021, 09:29:01 AM

This was resolved by doubling lines of 3V3 and GND on FFC cable by short cut R9 and R10 on matrix orbital board...

Title: Re: ESD 4.10 display instabilities
Post by: BRT Community on February 24, 2021, 12:20:14 PM

Hello,

Glad you have resolved the issue.

Best Regards,
BRT Community.