Hello Jerome,
Thank you for your question.
On the following:
Can I ask if you are seeing the INT_N pin assert for INT_SWAP or INT_CMDEMPTY, or are you simply reading the REG_INT_FLAGS register and seeing these flags are also set when for example a INT_TOUCH interrupt is triggered?
The REG_INT_FLAGS register keeps track of the available interrupt sources on the IC, and will set the flag accordingly for each source irrespective of the flags being masked by REG_INT_MASK. When REG_INT_EN is 1, INT_N is driven low when any of the interrupt flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK. Basically the flag will set for a given interrupt source when the given scenario for that flag happens, the mask is then used to tell the INT_N pin which flags it should assert for.
Best Regards,
BRT Community
Thank you for your question.
On the following:
Quote from: jipihorn on October 08, 2026, 01:34:05 PMHowever, whatever value I put here, I still get other interrupts like INT_SWAP or INT_CMDEMPTY.
Can I ask if you are seeing the INT_N pin assert for INT_SWAP or INT_CMDEMPTY, or are you simply reading the REG_INT_FLAGS register and seeing these flags are also set when for example a INT_TOUCH interrupt is triggered?
The REG_INT_FLAGS register keeps track of the available interrupt sources on the IC, and will set the flag accordingly for each source irrespective of the flags being masked by REG_INT_MASK. When REG_INT_EN is 1, INT_N is driven low when any of the interrupt flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK. Basically the flag will set for a given interrupt source when the given scenario for that flag happens, the mask is then used to tell the INT_N pin which flags it should assert for.
Best Regards,
BRT Community