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Topics - durian

Pages: [1]
1
Discussion - EVE / Font baseline metrics
« on: June 01, 2023, 10:58:12 PM »
Does any one have the baseline value (number of pixels from the bottom of the bitmap to the font's baseline) for each of the BT817/8 built-in fonts? I'd like to use that information to better align different size fonts.

mike

2
Discussion - EVE / 1.2V regulator quiescent current draw
« on: May 03, 2023, 05:46:07 PM »
On the BT818Q, I notice that the internal regulator still produces 1.2V on VOUT1V2 when the system is in POWERDOWN state. I'm trying to determine how much current the chip draws when in POWERDOWN and need to factor in the quiescent current draw from the regulator. I can't find this value in the datasheet. Is it included in the Icc1 figure shown in table 6-3? If not, can you provide it?

Also, table 6-3 show the maximum voltage for VCCIO2 is 2.75V. This conflicts with other parts of the datasheet that explicitly state that 3.3V can be applied to VCCIO2. I believe it is table 6-3 that is incorrect.

Thank you,
mike

3
Discussion - EVE / BEGIN(RECTS) primitive and LINE_WIDTH
« on: November 10, 2021, 10:28:14 PM »
Section 2.10.4 of the AN_033 programming guide says the current line width is used to round the corners when using the BEGIN(RECTS) primitive. It says, "Line width size is used for corner curvature, LINE_WIDTH pixels are added in both directions in addition to the rectangle dimension".

How does one get square corners, then? It would seem setting LINE_WIDTH to 0 would create a rectangle with square corners at exactly the size specified by the VERTEX2F() coordinates. But when I try that, the rectangle isn't drawn at all. Do I need to use a LINE_WIDTH of 1 pixel and then shrink my rectangle by 0.5 pixel at each coordinate? That seems rather awkward.

Is it better to avoid using BEGIN(RECTS) entirely and instead use SCISSOR and CLEAR to create rectangles?

4
Discussion - EVE / EVE Asset Converter failing
« on: November 03, 2021, 11:39:42 PM »
I'm trying to use the EVE Asset Converter to convert some png file to L4. I'm running version 2.1.0-rc2.

Here is an example from the log:
----------------------------------------------------------------------
C:/EAB/Input/diving_16.png conversion is in progress...
Conversion failed!
EXCEPTION IN (img_cvt.py, LINE 942 ""): [Errno 13] Permission denied: 'output.txt'

Traceback (most recent call last):
  File "img_cvt.py", line 942, in image_convert
  File "img_cvt.py", line 799, in run
PermissionError: [Errno 13] Permission denied: 'output.txt'


It's not showing me the full path to output.txt, so I don't know why it can't create the file. A folder called SampleApp is created in the output folder and it contains a ReadMe.txt and a few subfolders, but that's it. I can't find anything that looks like it might be the output from my converted image.

I can't locate img_cvt.py in EAB executable folder either, so I'm not able to dig into this any further on my own.

On a related note, if the asset builder is written in Python, having the source would be very helpful. Then I could run it directly under MacOS. A command line conversion utility would be especially handy.

5
Discussion - EVE / BT818 PCLK settings
« on: September 23, 2021, 09:32:38 PM »
I've got a BT818 on a board of mine and I'm seeing some weird things with respect to the PCLK timing.

1)
The REG_PCLK_FREQ register values don't agree with the datasheet when set by CMD_PCLKFREQ. For example, if I request a frequency of 36 MHz, REG_PCLK_FREQ gets set to 0x461. If you were to interpret that according to the data sheet, you'd get a frequency of 36 MHz, but the range (found in bits 10:9) are 10. That implies a range of 80 - 160 MHz. If we repeat the exercise, but with a frequency of 72 MHz, REG_PCLK_FREQ is 0x8c1 which has a range of 00 which is 20 - 40 MHz.

I think the real range bits are found in bits 11:10, not 10:9. But even then, the range for 36 MHz would be 01, which is 40 - 80 MHz. 36 MHz is below that. Similarly, a clock of 72 MHz gives a range value of 10, which is 80 - 160 MHz. 72 MHz is also below that range.

I'm not sure what's going on here, but the datasheet does not seem to agree with the results from CMD_PCLKFREQ.

2)
When I put a scope on the PCLK output, pin 39, I see a clock that is about half what was programmed. Does data get clocked out on both rising and falling edges? And if so, is that standard? I'm running the output of the BT818 into a TFP410 to create an HDMI signal and I think that chip expects only one pixel per clock cycle, not two. Can anyone explain to me what's going on here?

Thanks,
mike

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