Some might have noticed it already, I uploaded a new library on Github: https://github.com/RudolphRiedel/EmbeddedVideoEngine
I had the idea of renaming my library for a while, "FT800-FT813" was just wrong for a while now.
However, renaming seemed to be a bit disruptive, so I created a new repository for V6 of my library and the name should be future-proof now. :-)
I was already using the name for a while now in the library.json for PlatformIO.

Yesterday I tested the Arduino example, made sure it compiles for all tagets (although a few are non functional like the one for BBC Microbit.
And then I tested ESP32-S2, Arduno UNO V3, Teensy 4.1, Raspberry Pi Pico and Metro M4 with both a RVT50H (BT817) and the VM820C.

Right now I have the VM820C with the 7" 1024x600 TFT up and running with an ATSAME51 after a fix to the DMA code, and I already checked it with a BT817.
As usual, no warnings with -Wall -Wextra -pedantic.

Before I was using a STM32F407, so most targets are covered by now, at least are compiling or actually are tested.

While the lib is feature complete for the BT820, this is not finished.
There are still a couple of things missing like configuring the memory size for the BT820, the LVDS output clock is merely working by chance now, Audio does not seem to be working at all, video input is unexplored...

Unfortunately there are no modules for sale with a BT820, as far as I know. And only one was anounced.

I also learned again that sourcing LCDs is still a major pain, these things are really not commodities, speaking of course for not buying in bulk from a company account, trying to aquire single units.

I implemented a couple more commands and got to CMD_WATCHDOG.

The watchdog command enables the watchdog timer and sets the watchdog reset intervals in clocks.
The watchdog flag in REG_BOOT_CFG register must be set.

C prototype
void cmd_watchdog ( uint32_t init_val );

Command layout
+0 CMD_WATCHDOG(0xFFFF FF83)
+4 init_val

Parameters
init_val
Watchdog timeout initialization value, in clocks. Must be a sensible value to prevent
watchdog being triggered prematurely.

Examples
To set the watchdog timeout every 72000000 clocks, which is 1 second on a 72 MHz system:
cmd_watchdog(72000000);

Adds watchdog timer to facilitate automatic correction.

The watchdog timer uses a 32-bit counter and is driven by the system clock. Hence, at default system
clock of 72 MHz, the maximum timeout period supported is 59.6s.
The watchdog timer begins and resets as it counts down from a user-defined initial value. Upon reaching
a count value of zero, the watchdog timer generates a system reset. The timer needs to be periodically
reset to the initial value to prevent the system reset from happening.
Refer to BRT_AN_086 BT82X Series Programming Guide for details on how to program the Watchdog
Timer using cmd_watchdog

That is practically all if it.
So yes, the watchdog system needs to be enabled during boot.
And it does a system reset - whatever "automatic correction" this is good for.
Then there is CMD_WATCHDOG which is documented to enable the watchdog and configure the timeout.
But there is no command like CMD_TRIGGER_WATCHDOG, so CMD_WATCHDOG is resetting the timer?

And if CMD_WATCHDOG really is the only command, does a CMD_WATCHDOG(0) disable the watchdog?

What safety requirements are covered by this?
If the EVE chip would crash hard, and I never encountered this, would the watchdog timer really not be affected?
And how would a reset help in this scenario? The host controller had to detect either way that the EVE chip is not answering anymore.
Ok, different scenario, the host controller crashes, how would resetting the EVE chip help? The host controller would still be dead.
So when the watchdog is not triggered by CMD_WATCHDOG, the screen goes dark?

What am I missing here?
If the EVE chip would be able to reset the host controller, that would be different, that would make the EVE chip an external watchdog controller and that could  be viewed as positive for the system safety.
But I would use a window-watchdog with challenge-response for such a task, preferably in a SBC.

One way to check is to perform a cmd_fssize.  Directories will return -1 for the size.

Well, yes and no, technically. :-)
The size is documented to be a uint32_t.

And I got a couple of steps further along now, my test code is using CMD_FSSOURCE, CMD_LOADIMAGE with OPT_FS and CMD_GETIMAGE
to load one of the files returned by CMD_FSDIR and then display it.
I also found OPT_TRUECOLOR during this.

I just added the functions for CMD_RESTORECONTEXT and CMD_SAVECONTEXT.
And I do not get it, what was the point of adding these as commands to the co-processor?

SAVE_CONTEXT and RESTORE_CONTEXT are display-list commands that were introduced with the FT800, IDs 0x22 and 0x23.
And executing these with the co-processor, like the rest of the display-list commands, never was an issue.

So instead of having the co-processor just copy over the commands to the display-list it now has to exectute the
command to write the same values to the display-list.
This really strikes me as weird.
And then these were the only display-list commands that got that privilege to be elevated to co-processor commands.

The picture is nice and stable, yes, I started to implement the new commands for the BT820. 

But I currently have an issue that I can not explain.
First I noticed that I need to place additional VERTEX_FORMAT(0) in my display list, somehow the setting is not persistent.
Then I noticed that the back-to-back CMD_TEXT in the snippet I am using with CMD_APPEND no longer work, only the first line is displayed.
And when checking with the logic analyzer I found that a single CMD_TEXT is keeping the command-co-pro busy for an unusual amount of time, like there is some issue.
When I interleave the CMD_TEXT with COLOR_RGB then all the lines are displayed, the co-pro still is busy with this for quite a while though.

Choosing the less complicated CMD_NUMBER I get the same:

EVE_cmd_dlstart();
EVE_color_rgb(BLACK);
EVE_cmd_number(10, 515, 26, 0, 12345);
EVE_cmd_number(10, 500, 26, 0, 12345);
EVE_execute_cmd();

Followed by:
num_dl_static = EVE_memRead16(REG_CMD_DL);
EVE_cmd_memcpy(MEM_DL_STATIC, EVE_RAM_DL, num_dl_static);

The result right now is that the second line is not completely displayed.
When I switch the order of the lines, the other one gets incorrectly displayed.

When I throw in an extra EVE_color_rgb(BLACK); between the two CMD_NUMBER, then both lines are displayed.
When I use a NOP one of the lines still get corrupted.

The resulting sequence for EVE_cmd_number(10, 515, 26, 0, 12345); is:
0xff 0x01 0x00 0x00 - write + REG_CMDB_WRITE
0x2a 0xff 0xff 0xff - CMD_NUMBER
0x0a 0x00 0x03 0x02 - x = 10, y = 515
0x1a 0x00 0x00 0x00 - font = 26, options = 0
0x39 0x30 0x00 0x00 - number = 12345

I still need to read out the resulting display list snippet and analyze it, but right now I do not see anything wrong with my code.

Hmm, I added the lines with x=110 to the main display list and also made the list use separate commands instead of using DMA,
the two lines are displayed just fine.
Then I checked my implementation of CMD_APPEND, nothing there, changed the target address for the snippet, no change.

Looks like the co-processor does not like to put commands in a display list anymore that is not meant to be displayed on it's own?
There is no CLEAR_COLOR_RGB or CLEAR for the snippet, as this is in the main display list.


Edit: I just modified my code to use CMD_NEWLIST/CMD_ENDLIST/CMD_CALLLIST which just stores the co-processor command instead of executing them.
And this works just fine, when executed in the context of the display list, both lines for CMD_NUMBER are displayed correctly.

After restoring the rest of my original code everything is executed as it should, I even can remove the two extra VERTEX_FORMAT(0) lines that
were necessary before.
I noticed in ESE that both CMD_NUMBER and CMD_TEXT switch to use SAVE_CONTEXT / VERTEX_FORMAT(2) when going beyond 511 on the B817/BT818.
And with the BT820 SAVE_CONTEXT is replaced with REGION.
Oh wait, that is the issue, the destination in REGION is absolute, not relative, so with CMD_APPEND destinations are pointing to the wrong address in the display list.

At least there is a workaround, although it is exclusive to BT817/BT818/BT820.
Makes me again wonder why VERTEX_FORMAT(0) is not just the default.

Additionally I found that CMD_NEWLIST is not finishing on it's own, REG_CMDB_SPACE never indicates that the FIFO is empty.
Only after I removed the busy check things worked.
This behaviour is not documented and something I should try on the BT817.

And I am celebrating the first stable output on a LCD from the BT820! 

I am still having a weird timing issue, the output of the 1024 x 600 image is only to 3/4 of the width of the screen.
And nothing I did to the timing parameters so far made that smaller or wider, it only changes from stable to chaos.

Edit:
And now I have the image stretched across the complete display area. 

Looks like my PixelClock was too low.
With some trial and error I ended up with NS = 7 and DIV = 4 - REG_LVDSTX_PLLCFG = 0x00300874
NS = 7 and DIV = 2 is not working.
NS = 7 and DIV = 3 to DIV = F is working, although it starts to flicker at DIV = B.
NS = 8 and DIV = F is not working, although this should only be a little higher than NS = 7 and DIV = F.

My guess is that the description of REG_LVDSTX_PLLCFG is not correct.
But I can not measure the resulting pixel clock directly, I do not have an oscilloscope here.

A new milestone. :-)

I got to the point in reverse engineering the PCB800182 deep enough to be confident to attach my LCD to - and nothing bad happened, no magic smoke. :-)
I also modified the 20pin LVDS cable that came with the PCB800182 to use a 30pin connector with a single LVDS channel to attach to the VM820C.

So I tried to wiggle my way thru the initialization sequence.
First issue, there are no timing parameters in the "datasheet" of the ER-TFT070-3 I bought - argh.
Well, I checked what I have used for the BT817 7" with 1024x600.
 
To configure the LVDS output I came up with this:

void configure_lvds(void)
{
    EVE_memWrite32(REG_RE_DEST, EVE_SWAPCHAIN_0);
    EVE_memWrite32(REG_RE_FORMAT, EVE_ARGB8);
    EVE_memWrite32(REG_RE_W, EVE_HSIZE);
    EVE_memWrite32(REG_RE_H, EVE_VSIZE);
    EVE_memWrite32(REG_DISP, 1);

    EVE_memWrite32(REG_LVDSTX_PLLCFG, setlvdspll_value(0, PLL_LOCK_PERIOD, 1, 10, 7)); /* 38.4 MHz * 10 / 8 = 48MHz */
    EVE_memWrite32(REG_LVDSTX_EN, LVDS_CH0_EN);

    EVE_memWrite32(REG_SC0_RESET, 1);
    EVE_memWrite32(REG_SC0_SIZE, 2);
    EVE_memWrite32(REG_SC0_PTR0, 10 << 20);
    EVE_memWrite32(REG_SC0_PTR1, 20 << 20);

//    EVE_memWrite32(REG_SC1_SIZE, 2);
//    EVE_memWrite32(REG_SC1_PTR0, SC1_PTR0_STARTADDR);
//    EVE_memWrite32(REG_SC1_PTR1, SC1_PTR1_STARTADDR);

//    EVE_memWrite32(REG_SC2_SIZE, 2);
//    EVE_memWrite32(REG_SC2_PTR0, SC2_PTR0_STARTADDR);
//    EVE_memWrite32(REG_SC2_PTR1, SC2_PTR1_STARTADDR);

    EVE_memWrite32(REG_SO_EN, 0);
    EVE_memWrite32(REG_SO_MODE, EVE_SO_MODE_2);
    EVE_memWrite32(REG_SO_SOURCE, EVE_SWAPCHAIN_0);
    EVE_memWrite32(REG_SO_FORMAT, EVE_ARGB8);
    EVE_memWrite32(REG_SO_EN, 1UL); /* enable scanout */

    DELAY_MS(10);

}

But I am not sure if I got all the necessary register, if the order of writing them is correct and if I chose
values for all registers that actually make sense.

And it is not working, or only somewhat a little bit working.
I do get a white screen with some artifacts in the end.

I am not even sure how this all makes sense so far.
Why is there a REG_RE_FORMAT and a REG_SO_FORMAT?

Making this all configureable will be a challenge. :-)


Edit: I modified things a bit, changed the timing, switched the clock to 51.2MHz as suggested in the display controller datasheet of the LCD I have.
I also added:
EVE_memWrite32(REG_LVDSTX_CTRL_CH0, 1); /* JEIDA/Format 1 Mapping for 24-bit, Single Pixel per Clock */

And I am reading REG_LVDSTX_ERR_STAT and REG_LVDSTX_STAT now.
REG_LVDSTX_ERR_STAT reads as 3 which means: UNDERFLOW_CH0 + OVERFLOW_CH0

Hmm? Schroedingers LVDS, empty and full at the same time? :-)

The value of REG_LVDSTX_STAT changes with the value I put in REG_LVDSTX_CTRL_CH0
REG_LVDSTX_CTRL_CH0 = 0 -> REG_LVDSTX_STAT = 0x000015d1
REG_LVDSTX_CTRL_CH0 = 1 -> REG_LVDSTX_STAT = 0x00001791
REG_LVDSTX_CTRL_CH0 = 2 -> REG_LVDSTX_STAT = 0x00000fd1
REG_LVDSTX_CTRL_CH0 = 3 -> REG_LVDSTX_STAT = 0x00000e31

Bit 0 set = LVDSPLL_LOCK / PLL locked - that sounds correct
Bit 4 set = LVDS_CH0_ACTIVE - looking good
Bit 5 to 8 = LVDS_CH0_UNDFCNT - 14/12/14/1
Bit 9 to 12 = LVDS_CH0_OVFCNT - 10/11/7/7

The display is configured to 8 bit per color, SELB is set to GND, so REG_LVDSTX_CTRL_CH0 should be set to 1 or 2 (default).

What am I doing wrong?