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Messages - Rudolph

Pages: [1] 2 3 ... 32
1
Discussion - EVE / Re: BT82x
« on: April 21, 2025, 05:53:00 PM »
Time for some torture-testing of the BT820. :-)

The attached image shows this code:

Code: [Select]
        int16_t xc0 = 0;
        int16_t yc0 = 0;
        uint16_t length = 3;
        static uint16_t increase = 0;
        uint32_t colors[] = {RED, ORANGE, GREEN, BLUE, YELLOW, MAGENTA, PURPLE, BLACK, 0xc0c0c0, BLUE_1};

        for(uint8_t arms = 0; arms < 12; arms++)
        {
            EVE_color_rgb(colors[arms]);
            EVE_begin(EVE_LINE_STRIP);
            for(uint8_t steps = 0; steps < 135; steps++)
            {
                EVE_polar_cartesian(length*steps, arms*30+steps*increase, &xc0, &yc0);
                EVE_vertex2f(xc0 + 450, yc0 + 320);
            }
            EVE_end();
        }

        static uint8_t delay = 0;

        delay ++;

        if(delay > 2)
        {
            delay = 0;
            increase += 3;
        }

12 Linestrips with 135 segments each, 6916 bytes in the SPI buffe, a display-list of >8100 bytes, takes 1.3ms to preprare the buffer.
And this runs continously now, changing constantly.

All I noticed was that it started to flicker when I increased the "steps" in the loop.
Not for every value of "increase" though.
The flickering goes away when I decrease the maximum "steps" or increase the time between display-list updates.
Right now I am running this as posted and refresh the display list every 75ms, so 13 changes per second.
So this put the render-engine into stress-mode, sort of.

Nice, this stupid level of useless complexity should be way beyond what a normal application can put out to render.  :)

2
Discussion - EVE / Re: BT82x
« on: April 21, 2025, 03:12:11 PM »
Some might have noticed it already, I uploaded a new library on Github: https://github.com/RudolphRiedel/EmbeddedVideoEngine
I had the idea of renaming my library for a while, "FT800-FT813" was just wrong for a while now.
However, renaming seemed to be a bit disruptive, so I created a new repository for V6 of my library and the name should be future-proof now. :-)
I was already using the name for a while now in the library.json for PlatformIO.

Yesterday I tested the Arduino example, made sure it compiles for all tagets (although a few are non functional like the one for BBC Microbit.
And then I tested ESP32-S2, Arduno UNO V3, Teensy 4.1, Raspberry Pi Pico and Metro M4 with both a RVT50H (BT817) and the VM820C.

Right now I have the VM820C with the 7" 1024x600 TFT up and running with an ATSAME51 after a fix to the DMA code, and I already checked it with a BT817.
As usual, no warnings with -Wall -Wextra -pedantic.

Before I was using a STM32F407, so most targets are covered by now, at least are compiling or actually are tested.

While the lib is feature complete for the BT820, this is not finished.
There are still a couple of things missing like configuring the memory size for the BT820, the LVDS output clock is merely working by chance now, Audio does not seem to be working at all, video input is unexplored...

Unfortunately there are no modules for sale with a BT820, as far as I know. And only one was anounced.

I also learned again that sourcing LCDs is still a major pain, these things are really not commodities, speaking of course for not buying in bulk from a company account, trying to aquire single units.

3
Discussion - EVE / Re: BT82x
« on: April 19, 2025, 10:46:17 AM »
I implemented CMD_LOADWAV and in order to test it I enable audio in BOOTCFG.
The screen stays black though.

The host command is correct, it changes from 0xff 0xe8 0xc0 0x00 0x00 to 0xff 0xe8 0xe0 0x00 0x00.
Things look normal on the logic analyzer, "only" the screen stays black.

I am not writing to any of the audio registers, including not using CMD_LOADWAV.
I even moved the buffers for the swapchains.

Is it possible that the audio engine is messing with the clock tree?

4
Discussion - EVE / Re: BT82x
« on: April 18, 2025, 09:36:17 PM »
I implemented a couple more commands and got to CMD_WATCHDOG.

Quote
The watchdog command enables the watchdog timer and sets the watchdog reset intervals in clocks.
The watchdog flag in REG_BOOT_CFG register must be set.

C prototype
void cmd_watchdog ( uint32_t init_val );

Command layout
+0 CMD_WATCHDOG(0xFFFF FF83)
+4 init_val

Parameters
init_val
Watchdog timeout initialization value, in clocks. Must be a sensible value to prevent
watchdog being triggered prematurely.

Examples
To set the watchdog timeout every 72000000 clocks, which is 1 second on a 72 MHz system:
cmd_watchdog(72000000);

Quote
Adds watchdog timer to facilitate automatic correction.

Quote
The watchdog timer uses a 32-bit counter and is driven by the system clock. Hence, at default system
clock of 72 MHz, the maximum timeout period supported is 59.6s.
The watchdog timer begins and resets as it counts down from a user-defined initial value. Upon reaching
a count value of zero, the watchdog timer generates a system reset. The timer needs to be periodically
reset to the initial value to prevent the system reset from happening.
Refer to BRT_AN_086 BT82X Series Programming Guide for details on how to program the Watchdog
Timer using cmd_watchdog

That is practically all if it.
So yes, the watchdog system needs to be enabled during boot.
And it does a system reset - whatever "automatic correction" this is good for.
Then there is CMD_WATCHDOG which is documented to enable the watchdog and configure the timeout.
But there is no command like CMD_TRIGGER_WATCHDOG, so CMD_WATCHDOG is resetting the timer?

And if CMD_WATCHDOG really is the only command, does a CMD_WATCHDOG(0) disable the watchdog?

What safety requirements are covered by this?
If the EVE chip would crash hard, and I never encountered this, would the watchdog timer really not be affected?
And how would a reset help in this scenario? The host controller had to detect either way that the EVE chip is not answering anymore.
Ok, different scenario, the host controller crashes, how would resetting the EVE chip help? The host controller would still be dead.
So when the watchdog is not triggered by CMD_WATCHDOG, the screen goes dark?

What am I missing here?
If the EVE chip would be able to reset the host controller, that would be different, that would make the EVE chip an external watchdog controller and that could  be viewed as positive for the system safety.
But I would use a window-watchdog with challenge-response for such a task, preferably in a SBC.

5
Discussion - EVE / Re: BT82x
« on: April 17, 2025, 10:07:36 PM »
Another day, another screen of progress. :-)

I just added CMD_LOADASSET and tried it with two fonts converted with EAB 3.0.
Loading from SD card is really nice.

I am wondering what is driving up the display-list so much.
EVE_cmd_cgradient(EVE_EDGE_ZERO, 300, 200, 200, 200, WHITE, PURPLE); - 140 bytes
EVE_cmd_arc(400, 300, 100, 110, 0, 16384); - 144 bytes
debug-output of 8 hex-numbers - 736 bytes

Ok then, most of it is for all the text.

6
Discussion - EVE / Re: BT82x
« on: April 17, 2025, 05:16:45 PM »
Quote
One way to check is to perform a cmd_fssize.  Directories will return -1 for the size.

Well, yes and no, technically. :-)
The size is documented to be a uint32_t.

And I got a couple of steps further along now, my test code is using CMD_FSSOURCE, CMD_LOADIMAGE with OPT_FS and CMD_GETIMAGE
to load one of the files returned by CMD_FSDIR and then display it.
I also found OPT_TRUECOLOR during this.

7
Discussion - EVE / Re: BT82x
« on: April 16, 2025, 10:03:16 PM »
I am trying out the SD card functions now and just successfully used CMD_FSDIR.

CMD_FSDIR "only" returns a bunch of names.
How can I find out which of these names are directories?

Edit: I implemented CMD_FSSIZE and the number returned for directories is 0xffffffff.
Well, yes, that matches the description of CMD_FSSIZE, that entry is not a file, so no file of that name was found.
And consequently CMD_FSREAD and CMD_FSSOURCE return 2 on folders for file-not-found.

So when the name is returned by CMD_FSDIR and CMD_FSSOURCE returns 2, then it is a folder.

8
Discussion - EVE / Re: BT82x
« on: April 15, 2025, 09:18:29 PM »
I just added the functions for CMD_RESTORECONTEXT and CMD_SAVECONTEXT.
And I do not get it, what was the point of adding these as commands to the co-processor?

SAVE_CONTEXT and RESTORE_CONTEXT are display-list commands that were introduced with the FT800, IDs 0x22 and 0x23.
And executing these with the co-processor, like the rest of the display-list commands, never was an issue.

So instead of having the co-processor just copy over the commands to the display-list it now has to exectute the
command to write the same values to the display-list.
This really strikes me as weird.
And then these were the only display-list commands that got that privilege to be elevated to co-processor commands.

9
Discussion - EVE / Re: BT82x
« on: April 15, 2025, 03:17:21 PM »
I just implemented CMD_RESULT and had an idea.

The register region has room for over 2100 registers in the BT820.
Documented are 155 right now and regardless of how many register are undocumented, it should be highly unlikely that
there are not plenty of unused slots.

Can we please reserve a bunch and name them like REG_USER0 to REG_USER9?

Why?
Because CMD_RESULT(REG_USER0) would be nicer than needing to find places in the memory map over and over again.

10
Discussion - EVE / Re: BT82x
« on: April 15, 2025, 10:12:08 AM »
The picture is nice and stable, yes, I started to implement the new commands for the BT820.  :)

But I currently have an issue that I can not explain.
First I noticed that I need to place additional VERTEX_FORMAT(0) in my display list, somehow the setting is not persistent.
Then I noticed that the back-to-back CMD_TEXT in the snippet I am using with CMD_APPEND no longer work, only the first line is displayed.
And when checking with the logic analyzer I found that a single CMD_TEXT is keeping the command-co-pro busy for an unusual amount of time, like there is some issue.
When I interleave the CMD_TEXT with COLOR_RGB then all the lines are displayed, the co-pro still is busy with this for quite a while though.

Choosing the less complicated CMD_NUMBER I get the same:

EVE_cmd_dlstart();
EVE_color_rgb(BLACK);
EVE_cmd_number(10, 515, 26, 0, 12345);
EVE_cmd_number(10, 500, 26, 0, 12345);
EVE_execute_cmd();

Followed by:
num_dl_static = EVE_memRead16(REG_CMD_DL);
EVE_cmd_memcpy(MEM_DL_STATIC, EVE_RAM_DL, num_dl_static);

The result right now is that the second line is not completely displayed.
When I switch the order of the lines, the other one gets incorrectly displayed.

When I throw in an extra EVE_color_rgb(BLACK); between the two CMD_NUMBER, then both lines are displayed.
When I use a NOP one of the lines still get corrupted.

The resulting sequence for EVE_cmd_number(10, 515, 26, 0, 12345); is:
0xff 0x01 0x00 0x00 - write + REG_CMDB_WRITE
0x2a 0xff 0xff 0xff - CMD_NUMBER
0x0a 0x00 0x03 0x02 - x = 10, y = 515
0x1a 0x00 0x00 0x00 - font = 26, options = 0
0x39 0x30 0x00 0x00 - number = 12345

I still need to read out the resulting display list snippet and analyze it, but right now I do not see anything wrong with my code.

Hmm, I added the lines with x=110 to the main display list and also made the list use separate commands instead of using DMA,
the two lines are displayed just fine.
Then I checked my implementation of CMD_APPEND, nothing there, changed the target address for the snippet, no change.

Looks like the co-processor does not like to put commands in a display list anymore that is not meant to be displayed on it's own?
There is no CLEAR_COLOR_RGB or CLEAR for the snippet, as this is in the main display list.


Edit: I just modified my code to use CMD_NEWLIST/CMD_ENDLIST/CMD_CALLLIST which just stores the co-processor command instead of executing them.
And this works just fine, when executed in the context of the display list, both lines for CMD_NUMBER are displayed correctly.

After restoring the rest of my original code everything is executed as it should, I even can remove the two extra VERTEX_FORMAT(0) lines that
were necessary before.
I noticed in ESE that both CMD_NUMBER and CMD_TEXT switch to use SAVE_CONTEXT / VERTEX_FORMAT(2) when going beyond 511 on the B817/BT818.
And with the BT820 SAVE_CONTEXT is replaced with REGION.
Oh wait, that is the issue, the destination in REGION is absolute, not relative, so with CMD_APPEND destinations are pointing to the wrong address in the display list.

At least there is a workaround, although it is exclusive to BT817/BT818/BT820.
Makes me again wonder why VERTEX_FORMAT(0) is not just the default.

Additionally I found that CMD_NEWLIST is not finishing on it's own, REG_CMDB_SPACE never indicates that the FIFO is empty.
Only after I removed the busy check things worked.
This behaviour is not documented and something I should try on the BT817.

11
Discussion - EVE / Re: BT82x
« on: April 14, 2025, 09:28:08 AM »
How do I use the touch engine?
As far as I understand it, setting bit 6 in SETBOOTCFG should be enough, this should enable the touch system and
during boot the touch system should do an auto-discovery to determine the touch controller connected.

My LCD does have a FT5316 and after connecting it to the VM820C it does nothing at all.
Reading REG_TOUCH_CONFIG returns 0x00000000, writing 0 or 0x381 does nothing either.

I can not calibrate and reading REG_TOUCH_RAW_XY returns 0xFFFFFFFF.

It should not be necessary to setup CTP_SCL/GPIO5, CPT_SDA/GPIO6, CTP_INT/GPIO7 or CTP_RST/GPIO8 in order to use the touch engine.
But then I can not find how to actually set this up anyways, how to configure them for alternate function or GPIO.

Edit: I soldered pins and to the FFC adapter I am using for the touch controller and looking at SCL, SDA and Reset with the logic analyzer.
And while the pins wiggle like expected for their function, the touch controller does not seem to answer.

What is odd though, when I write 0x381UL to REG_TOUCH_CONFIG to setup a FocalTech device, the lines are just dead.
SCL is Low - really odd for an open collector ouput with pullup-resistor, SDA and Reset are high.

When I write 0x380UL to REG_TOUCH_CONFIG, which should not do much according to the register description,
apparently auto discovery is triggered, Reset is pulled low, then there is a pause and then there is one or two byte transfers on SCL/SDA.
Same thing happens when not writing to REG_TOUCH_CONFIG or when writing 0.

Oddly I also see 311ms periods with SCL just low like this, even when I disconnect the CTP.

Maybe my touch controller is toast, but what the BT820 does is not looking correct either.

Looks like I need to check the touch controller with an Arduino, there was some I2C scan sketch somewhere.
Edit: I did just that, I have an Arduino UNO running at 3.3V with 4k7 pullup resistors to 3.3V scan the I2C right now, connected to the CTP of the display as written on it's FFC cable: 1 = GND, 2 = SDA, 3 = SCL, 7 = VDD - and nothing is found.
Strange.


Edit: I found the issue, I do have working touch now.  ;D

The connector on the 10pin FFC adapter board I am using looks like is contacting on both sides of the cable,
but it definately is only contacting on the bottom side.
The cable for the CTP has the contacts on the top side...

Have two fotos to celebrate. :-)
Yes, I noticed that the backlight is a bit dim, but I can't control it by software and only set it to 20mA, maybe I'll add another resistor in parallel later.


Edit: I just put up a repository with the information from reverse engineering this display adapter: https://github.com/RudolphRiedel/PCB800182_LCD_Adapter

12
Discussion - EVE / Re: BT82x
« on: April 13, 2025, 06:21:21 PM »
And I am celebrating the first stable output on a LCD from the BT820!  :)

I am still having a weird timing issue, the output of the 1024 x 600 image is only to 3/4 of the width of the screen.
And nothing I did to the timing parameters so far made that smaller or wider, it only changes from stable to chaos.

Edit:
And now I have the image stretched across the complete display area.  :)

Looks like my PixelClock was too low.
With some trial and error I ended up with NS = 7 and DIV = 4 - REG_LVDSTX_PLLCFG = 0x00300874
NS = 7 and DIV = 2 is not working.
NS = 7 and DIV = 3 to DIV = F is working, although it starts to flicker at DIV = B.
NS = 8 and DIV = F is not working, although this should only be a little higher than NS = 7 and DIV = F.

My guess is that the description of REG_LVDSTX_PLLCFG is not correct.
But I can not measure the resulting pixel clock directly, I do not have an oscilloscope here.

13
Discussion - EVE / Re: BT82x
« on: April 13, 2025, 12:36:19 PM »
I am getting closer,but the output on my LCD still is corrupted.
But at least I can see that there is something going on now, I am using CMD_LOGO and there is some movement in the chaos for a couple of seconds.

I found that my function of calculating the value for REG_LVDSTX_PLLCFG was completely broken.
But after fixing it, it still does not work.
As it turns out, the description for REG_LVDSTX_PLLCFG in the programming guide is wrong.
The reset default value is 0x00300877 - and that is correctly stated.
"Table 18 – LVDSTX Clock Configuration" can not be correct though, first indication is that 15 and 8 are not the default values.

And in the datasheet I finally found this:
Quote
4.12.2 Phase Locked Loop
There are 4 Phase Locked Loops (PLLs) inside the chip; the system PLL (PLL1), LVDSPLL (PLL2), DDRPLL
(PLL3) and the DDR PHYPLL (PLL4)
The system PLL receives the input clock from the oscillator and produce both the system clock and the
LVDSTX clock.
The LVDS PLL takes the input clock from the LVDSTX clock and generates the LVDS fast clock.
The DDRPLL and the DDR PHYPLL are used to generate clock for the DDR interface.

And while this not quite cleary written, it shows that that input for the LVDSPLL (PLL2) is not the Oscillator with 38.4MHz,
but the system clock that is generated by the system PLL (PLL1) and which defaults to 72MHz.

So when I tried to use NS = 8 and CLKDIV = 5 in order to setup the LVDSTX clock to 51.2MHz, I was setting it up to 96MHz instead,
which is out of spec for the LCD I have.

The default value of 0x00300877 should result in a pixel clock of 63MHz, however LVDSPLL_CK is configured incorrectly to 0b01, if I am understanding the
programming guide correctly, that would be for a CTLCLK range of 200MHz to 400MHz, NS = 7 and input = 72MHz results in 504MHz though.
So a valid default value should have been 0x00301077.

And with 72MHz as input for the LVDSTX PLL I can not set the clock to 51.2MHz - pretty close to 51.43MHz though.

There is no maximum range given for either SYSPLL_CKS or LVDSPLL_CK, according to REG_SYS_CFG and REG_LVDS_PLLCFG it might be
400MHz to 800MHz for SYSPLL_CKS and 200MHz to 800MHz for LVDSPLL_CK.
That would put the valid range for NS of system clock to a range of 11 to 20 while 72MHz might be the the highest Systemclock allowed.

And with 72MHz system clock the allowed range for NS of the LVDSTX PLL would be 3 to 12.
But well, the allowed range for the system clock might be 36MHz to 72MHz.

If I am correct on this, please provide updated versions of both the DS_BT820 and BRT_AN_086_BT82X-Series-Programming-Guide
with more and accurate information.

Oh yes, I also found BRT_AN_092-BT820-Hardware-Design-Example, unfortunately there is nothing in there on setting up LVDSTX.

Another source of information could have been EVE Screen Editor.
However, v5.0.0 only shows a fraction of the the registers in RAM_REG and there are no built-in settings for connecting to a 1024x600 LCD.

14
Discussion - EVE / Re: BT82x
« on: April 09, 2025, 10:55:27 PM »
A new milestone. :-)

I got to the point in reverse engineering the PCB800182 deep enough to be confident to attach my LCD to - and nothing bad happened, no magic smoke. :-)
I also modified the 20pin LVDS cable that came with the PCB800182 to use a 30pin connector with a single LVDS channel to attach to the VM820C.

So I tried to wiggle my way thru the initialization sequence.
First issue, there are no timing parameters in the "datasheet" of the ER-TFT070-3 I bought - argh.
Well, I checked what I have used for the BT817 7" with 1024x600.
 
To configure the LVDS output I came up with this:

Code: [Select]
void configure_lvds(void)
{
    EVE_memWrite32(REG_RE_DEST, EVE_SWAPCHAIN_0);
    EVE_memWrite32(REG_RE_FORMAT, EVE_ARGB8);
    EVE_memWrite32(REG_RE_W, EVE_HSIZE);
    EVE_memWrite32(REG_RE_H, EVE_VSIZE);
    EVE_memWrite32(REG_DISP, 1);

    EVE_memWrite32(REG_LVDSTX_PLLCFG, setlvdspll_value(0, PLL_LOCK_PERIOD, 1, 10, 7)); /* 38.4 MHz * 10 / 8 = 48MHz */
    EVE_memWrite32(REG_LVDSTX_EN, LVDS_CH0_EN);

    EVE_memWrite32(REG_SC0_RESET, 1);
    EVE_memWrite32(REG_SC0_SIZE, 2);
    EVE_memWrite32(REG_SC0_PTR0, 10 << 20);
    EVE_memWrite32(REG_SC0_PTR1, 20 << 20);

//    EVE_memWrite32(REG_SC1_SIZE, 2);
//    EVE_memWrite32(REG_SC1_PTR0, SC1_PTR0_STARTADDR);
//    EVE_memWrite32(REG_SC1_PTR1, SC1_PTR1_STARTADDR);

//    EVE_memWrite32(REG_SC2_SIZE, 2);
//    EVE_memWrite32(REG_SC2_PTR0, SC2_PTR0_STARTADDR);
//    EVE_memWrite32(REG_SC2_PTR1, SC2_PTR1_STARTADDR);

    EVE_memWrite32(REG_SO_EN, 0);
    EVE_memWrite32(REG_SO_MODE, EVE_SO_MODE_2);
    EVE_memWrite32(REG_SO_SOURCE, EVE_SWAPCHAIN_0);
    EVE_memWrite32(REG_SO_FORMAT, EVE_ARGB8);
    EVE_memWrite32(REG_SO_EN, 1UL); /* enable scanout */

    DELAY_MS(10);

}

But I am not sure if I got all the necessary register, if the order of writing them is correct and if I chose
values for all registers that actually make sense.

And it is not working, or only somewhat a little bit working.
I do get a white screen with some artifacts in the end.

I am not even sure how this all makes sense so far.
Why is there a REG_RE_FORMAT and a REG_SO_FORMAT?

Making this all configureable will be a challenge. :-)


Edit: I modified things a bit, changed the timing, switched the clock to 51.2MHz as suggested in the display controller datasheet of the LCD I have.
I also added:
EVE_memWrite32(REG_LVDSTX_CTRL_CH0, 1); /* JEIDA/Format 1 Mapping for 24-bit, Single Pixel per Clock */

And I am reading REG_LVDSTX_ERR_STAT and REG_LVDSTX_STAT now.
REG_LVDSTX_ERR_STAT reads as 3 which means: UNDERFLOW_CH0 + OVERFLOW_CH0

Hmm? Schroedingers LVDS, empty and full at the same time? :-)

The value of REG_LVDSTX_STAT changes with the value I put in REG_LVDSTX_CTRL_CH0
REG_LVDSTX_CTRL_CH0 = 0 -> REG_LVDSTX_STAT = 0x000015d1
REG_LVDSTX_CTRL_CH0 = 1 -> REG_LVDSTX_STAT = 0x00001791
REG_LVDSTX_CTRL_CH0 = 2 -> REG_LVDSTX_STAT = 0x00000fd1
REG_LVDSTX_CTRL_CH0 = 3 -> REG_LVDSTX_STAT = 0x00000e31

Bit 0 set = LVDSPLL_LOCK / PLL locked - that sounds correct
Bit 4 set = LVDS_CH0_ACTIVE - looking good
Bit 5 to 8 = LVDS_CH0_UNDFCNT - 14/12/14/1
Bit 9 to 12 = LVDS_CH0_OVFCNT - 10/11/7/7

The display is configured to 8 bit per color, SELB is set to GND, so REG_LVDSTX_CTRL_CH0 should be set to 1 or 2 (default).

What am I doing wrong?

15
Discussion - EVE / Re: BT82x
« on: April 05, 2025, 01:54:56 PM »
Ok, I am trying to figure out how to configure the display output and I doubt now that my display will show anything by tomorrow.

With host command RST_PULSE removed, is using the pin PD_N / RST_N mandatory now?

What is the minimum recommended time to wait after raising RST_N?

Any suggestions on what to do if rd32() fails to read due to not receiving 0x01?

How to actually configure the display output? There is close to nothing so far in the programming guide.
What needs to be configured and in what order?
How do the older register like REG_HSYNC0 interact with the LVDSTX settings?
How do the REG_RE_ and REG_SO_ registers interact with this?

Where in the initialization sequence is setting up the Swap Chains supposed to be placed?
How is the size of a SwapChain buffer calculated? REG_SCx_SIZE holds the number of buffers, not their size. From REG_RE_FORMAT, REG_RE_H and REG_RE_W?

Why do the examples use different names for the registers than the programming guide? e.g. REG_LVDS_* -> REG_LVDSTX_*

How is the watchdog used?

With REG_TOUCH_RZTHRESH gone, how to configure the sensitivity of resistive touch?

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