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Messages - BRT Community

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256
Discussion - EVE / Re: Problem disabling Font Cache of BT817
« on: November 12, 2021, 03:29:25 PM »
Hello,

Thankyou for the update, I don't see any issues with this approach initially but I will double check this with the development team.

Best Regards,
BRT Community

257
Discussion - EVE / Re: Problem disabling Font Cache of BT817
« on: November 12, 2021, 11:48:45 AM »
Hello,

We found after some testing that cmd_fontcache does NOT implement the disable mechanism. We are currently updating the programming guide accordingly.

As such  cmd_fontcache(255, ptr, number) will not work as expected.

Here is the workaround:
   
1)   use cmd_coldstart() which clears all the font state, including the font handle with cache enabled.
Or
2)   avoid using the font handle for any other non-cached font.


Best Regards,
BRT Community

258
Hello,

Thank you for the suggestion!

Best Regards,
BRT Community

259
Discussion - EVE / Re: BT818 PCLK settings
« on: November 04, 2021, 09:55:47 AM »
Hi,

To convert VESA timing to EVE RGB registers, you can refer to BT817/8 Datasheet page 26 Table 4-14 and fig 4-6 https://brtchip.com/wp-content/uploads/Support/Documentation/Datasheets/ICs/EVE/DS_BT817_8.pdf; or AN_336 page 6-7 https://brtchip.com/wp-content/uploads/Support/Documentation/Application_Notes/ICs/EVE/AN_336_FT8xx-Selecting-an-LCD-Display.pdf.

CYCLE = active + blank
SIZE = active
OFFSET = sync + back porch ( = blank - front porch)
SYNC0 = 0
SYNC1 = sync

For the given VESA timing for 640x480@60Hz, the recommended BT818 register values are:
HCYCLE = 800
HSIZE = 640
HOFFSET = 144
HSYNC0 = 0
HSYNC1 = 96
VCYCLE = 525
VSIZE = 480
VOFFSET = 35
VSYNC0 = 0
VSYNC1 = 2

PCLK = 1
PCLK_FREQ = 0x0D14 (the closed pixel frequency that BT818 can supply is 25.5MHz)
PCLK_POL = 0 or 1, depend on the HDMI chip clock porality.

1) Does the BT818 render each line during the blanking period (HOFFSET)?

Valid RGB data will start to clock out after HOFFSET, indicated by DE going to active.

2) Why does HCYCLE need to be greater than HSIZE + HOFFSET, instead of greater than or equal to HSIZE + HOFFSET? I don't see any cycles in the Figure 4-6 RGB Timing Waveforms from the datasheet that would allow HOFFSET < HCYCLE - HSIZE.

HOFFSET is not the whole blanking period. It includes sync and back porch, and may include part of the front porch(HSYNC0) . Datasheet Table 4-14 has provided requirements that HOFFSET must be < HCYCLE – HSIZE.

3) Is the blanking period (HOFFSET) not sufficient for rendering?

BT818 scanout does not depend on blanking. The blanking is required by the display panel.

4) If it is not sufficient, how do I calculate how much addition time is required?

Blanking timing is provided by display panel. If the display panel allows a range of blanking period, it is recommended to set BT818 total blanking to the maximum allowed by the display panel, thus more line time for graphics processing.

Best regards

BRT Community

260
Discussion - EVE / Re: Problem disabling Font Cache of BT817
« on: November 03, 2021, 03:26:34 PM »
Hello,

Thanks for the update.
I will follow up with any suggestions the hardware/software team may have on this if applicable.

Best Regards,
BRT community

261
Discussion - EVE / Re: Problem disabling Font Cache of BT817
« on: November 02, 2021, 12:11:28 PM »
Hello,

I've had a quick update from the development team noting that the are unable to re-produce this error and suspect it may be hardware related (presumably the IC and not the PCB).
I'm seeking some further advice on methods to debug this currently.

Best Regards,
BRT Community.

262
Discussion - EVE / Re: BT818 PCLK settings
« on: November 01, 2021, 02:38:41 PM »
Hi,

If you provide the display resolution, we can recommend register settings. Otherwise, please point out which VESA setting is not working.

For HDMI displays, there must be a RGB to HDMI bridge chip between BT818 and HDMI connector. Please make sure the HDMI chip is properly configured.

Best regards

BRT Community

263
Discussion - EVE / Re: BRT_AN_033_BT81X_Series_Programming_Guide.pdf
« on: November 01, 2021, 02:13:02 PM »
Hi Rudolph,

Thanks again for all your feedback on the guide, it is very much appreciated.

We'll look at your points which you raised here and include them in the next release which will be made soon,

Best Regards, BRT Community

264
Discussion - EVE / Re: Problem disabling Font Cache of BT817
« on: October 29, 2021, 03:26:23 PM »
Hello,

Thank you for the details.

I think in this case we can safely assume that there isn't an issue with the board design itself, but the difference in behaviour between the ICs is curious.

I will double check with the development team if there are any prerequisites when issuing the CMD_FONTCACHE = 255.

Best Regards,
BRT Community

265
Discussion - EVE / Re: Problem disabling Font Cache of BT817
« on: October 28, 2021, 03:49:40 PM »
Hello,

Thank you for your post.

However, it sounds like the co-processor is getting stuck in this scenario. I am also curious as to why this issue is only apparent for one of the three ICs you have to hand.
Are you using one of our development boards, or a board of your own design?

Are the chip markings on all three of the ICs the same?

Best Regards,
BRT Community

266
Discussion - EVE / Re: Modifying RAM_DL on the fly
« on: October 27, 2021, 04:58:51 PM »
Hi,

I'm glad to hear you got it working!

As you mentioned, the call list and append work differently compared to editing a live bitmap and are intended for constructing a display list. The macro feature would be ideal for your requirement however there are only two of these.

The device has other features such as animation but for the vertex method it sounds like you have found a good solution.

Best regards

BRT Community

267
Discussion - EVE / Re: BT818 PCLK settings
« on: October 27, 2021, 04:58:48 PM »
Hi,

On many TFT displays a range of values are permitted allowing some flexibility, if yours are different could you advise what screen you are using and a bit more information on it?

Best regards

BRT Community

268
General Discussion / Re: How to read REG_ID register
« on: October 22, 2021, 01:53:50 PM »
Hi,

We used an NXP K64 FRDM as a porting guide for our BRT_AN_025 code although it was on the older Kinetis Design Studio.

Its still under test and could be optimised on the MCU specific part but it does run, Here is the code in case its of any help,

We had to remove the includes folder due to the attachment size but these were all the standard ones included with a new K64 project,

Best Regards, BRT Community

269
General Discussion / Re: How to read REG_ID register
« on: October 19, 2021, 03:22:34 PM »
Hi Geethanjali,
Recommend to check the hardware connections as it might be that there is some issue there if you are using the start-up routines which work well for Rudolph

Hi Rudolph,
Not at all, you're giving very good advice and help as always.
Quote
And since I am obviously ignored, I am out.

Best Regards, BRT Community


270
General Discussion / Re: How to read REG_ID register
« on: October 19, 2021, 01:23:59 PM »
Hi,
GPIO was for the original EVE devices and is retained for backward compatibility,  but GPIOX is an extended one on later versions. Therefore, unless you need backward compatibility you can use the GPIOX ones.
Best Regards, BRT Community

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