Hi,
To convert VESA timing to EVE RGB registers, you can refer to BT817/8 Datasheet page 26 Table 4-14 and fig 4-6
https://brtchip.com/wp-content/uploads/Support/Documentation/Datasheets/ICs/EVE/DS_BT817_8.pdf; or AN_336 page 6-7
https://brtchip.com/wp-content/uploads/Support/Documentation/Application_Notes/ICs/EVE/AN_336_FT8xx-Selecting-an-LCD-Display.pdf.
CYCLE = active + blank
SIZE = active
OFFSET = sync + back porch ( = blank - front porch)
SYNC0 = 0
SYNC1 = sync
For the given VESA timing for 640x480@60Hz, the recommended BT818 register values are:
HCYCLE = 800
HSIZE = 640
HOFFSET = 144
HSYNC0 = 0
HSYNC1 = 96
VCYCLE = 525
VSIZE = 480
VOFFSET = 35
VSYNC0 = 0
VSYNC1 = 2
PCLK = 1
PCLK_FREQ = 0x0D14 (the closed pixel frequency that BT818 can supply is 25.5MHz)
PCLK_POL = 0 or 1, depend on the HDMI chip clock porality.
1) Does the BT818 render each line during the blanking period (HOFFSET)?
Valid RGB data will start to clock out after HOFFSET, indicated by DE going to active.
2) Why does HCYCLE need to be greater than HSIZE + HOFFSET, instead of greater than or equal to HSIZE + HOFFSET? I don't see any cycles in the Figure 4-6 RGB Timing Waveforms from the datasheet that would allow HOFFSET < HCYCLE - HSIZE.
HOFFSET is not the whole blanking period. It includes sync and back porch, and may include part of the front porch(HSYNC0) . Datasheet Table 4-14 has provided requirements that HOFFSET must be < HCYCLE – HSIZE.
3) Is the blanking period (HOFFSET) not sufficient for rendering?
BT818 scanout does not depend on blanking. The blanking is required by the display panel.
4) If it is not sufficient, how do I calculate how much addition time is required?
Blanking timing is provided by display panel. If the display panel allows a range of blanking period, it is recommended to set BT818 total blanking to the maximum allowed by the display panel, thus more line time for graphics processing.
Best regards
BRT Community