Hi,

It will depend on which display you have and which EVE family device you use,

The Programmers guide for your EVE device will have details of the start-up sequence e.g. see section 2.4 if you use BT81x
https://brtchip.com/wp-content/uploads/2021/09/BRT_AN_033_BT81X-Series-Programming-Guide.pdf

It is also best to check the documentation for your module as it may have additional requirements.

Here is a rough start-up sequence just as a guide,


// Reset the display
MCU_Delay_20ms();
HAL_PowerDown(1);
MCU_Delay_20ms();
HAL_PowerDown(0);
MCU_Delay_20ms();

#if (defined EVE1_ENABLE)
// FT80x_selection - FT80x modules generally use external crystal
// You can also send the host command to set the PLL here if you want to change it from the default of 48MHz (FT80x) or 60MHz (FT81x)
// Clock selection and clock rate selection will put EVE to sleep and so must be before the Active command
// for example:
HAL_HostCmdWrite(0x44, 0x00); // 0x44 = HostCMD_CLKEXT
HAL_HostCmdWrite(0x62, 0x00); // 0x64 = HostCMD_CLK48M
#endif

#if defined (EVE3_ENABLE) || defined (EVE4_ENABLE)
// can optionally set to 72MHz system clock here
// In this case also adjust REG_FREQUENCY a few lines down from here in this file
HAL_HostCmdWrite(0x44, 0x00); // 0x44 = HostCMD_CLKEXT
HAL_HostCmdWrite(0x61, 0x46);
#endif

#if defined (EVE2_ENABLE) || defined (EVE3_ENABLE)|| defined (EVE4_ENABLE)
HAL_HostCmdWrite(0x68, 0x00); // Reset
#endif


// Set active
HAL_HostCmdWrite(0, 0x00);

// MCU_Delay_500ms(); // Optional delay can be commented so long as we check the REG_ID and REG_CPURESET

// Read REG_ID
while ((val = HAL_MemRead8(EVE_REG_ID)) != 0x7C)
{
}

// Ensure CPUreset register reads 0 and so FT8xx is ready
while (HAL_MemRead8(EVE_REG_CPURESET) != 0x00)
{
}

#if defined (EVE3_ENABLE) || defined (EVE4_ENABLE)
HAL_MemWrite32(EVE_REG_FREQUENCY, 72000000);
#endif

// LCD display parameters
// Active width of LCD display
HAL_MemWrite16(EVE_REG_HSIZE,   EVE_DISP_WIDTH);
// Total number of clocks per line
HAL_MemWrite16(EVE_REG_HCYCLE,  EVE_DISP_HCYCLE);
// Start of active line
HAL_MemWrite16(EVE_REG_HOFFSET, EVE_DISP_HOFFSET);
// Start of horizontal sync pulse
HAL_MemWrite16(EVE_REG_HSYNC0,  EVE_DISP_HSYNC0);
// End of horizontal sync pulse
HAL_MemWrite16(EVE_REG_HSYNC1,  EVE_DISP_HSYNC1);
// Active height of LCD display
HAL_MemWrite16(EVE_REG_VSIZE,   EVE_DISP_HEIGHT);
// Total number of lines per screen
HAL_MemWrite16(EVE_REG_VCYCLE,  EVE_DISP_VCYCLE);
// Start of active screen
HAL_MemWrite16(EVE_REG_VOFFSET, EVE_DISP_VOFFSET);
// Start of vertical sync pulse
HAL_MemWrite16(EVE_REG_VSYNC0,  EVE_DISP_VSYNC0);
// End of vertical sync pulse
HAL_MemWrite16(EVE_REG_VSYNC1,  EVE_DISP_VSYNC1);
// Define RGB output pins
HAL_MemWrite8(EVE_REG_SWIZZLE,  EVE_DISP_SWIZZLE);
// Define active edge of PCLK
HAL_MemWrite8(EVE_REG_PCLK_POL, EVE_DISP_PCLKPOL);
// Turn on or off CSpread
HAL_MemWrite8(EVE_REG_CSPREAD,  EVE_DISP_CSPREAD);
// Turn on or off Dither
HAL_MemWrite8(EVE_REG_DITHER,  EVE_DISP_DITHER);



// Write first display list
HAL_MemWrite32((EVE_RAM_DL + 0), EVE_ENC_CLEAR_COLOR_RGB(0,0,0));
HAL_MemWrite32((EVE_RAM_DL + 4), EVE_ENC_CLEAR(1,1,1));
HAL_MemWrite32((EVE_RAM_DL + 8), EVE_ENC_DISPLAY());
HAL_MemWrite8(EVE_REG_DLSWAP, EVE_DLSWAP_FRAME);


// Read the  GPIO register for a read/modify/write operation
regGpio = HAL_MemRead8(EVE_REG_GPIO);
// set bit 7 of  GPIO register (DISP) - others are inputs
regGpio = regGpio | 0x80;
// Enable the DISP signal to the LCD panel
HAL_MemWrite8(EVE_REG_GPIO, regGpio);



// Write the PCLK or PCLK_FREQ register
// If setting PCLK_FREQ then also set REG_PCLK to 1 to enable extsync mode
#if (defined EVE4_ENABLE) && (defined SET_PCLK_FREQ)
HAL_MemWrite16(EVE_REG_PCLK_FREQ,  EVE_DISP_PCLK_FREQ);
HAL_MemWrite8(EVE_REG_PCLK, 1);
# else
// Now start clocking data to the LCD panel
HAL_MemWrite8(EVE_REG_PCLK, EVE_DISP_PCLK);
#endif


HAL_MemWrite8(EVE_REG_PWM_DUTY, 127);

// ---------------------- Touch and Audio settings -------------------------

// Eliminate any false touches
HAL_MemWrite16(EVE_REG_TOUCH_RZTHRESH, 1200);

// turn recorded audio volume down
HAL_MemWrite8(EVE_REG_VOL_PB, EVE_VOL_ZERO);
// turn synthesizer volume down
HAL_MemWrite8(EVE_REG_VOL_SOUND, EVE_VOL_ZERO);
// set synthesizer to mute
HAL_MemWrite16(EVE_REG_SOUND, 0x6000);

// --------------------- Clear screen ready to start -----------------------
EVE_LIB_BeginCoProList();
EVE_CMD_DLSTART();
EVE_CLEAR_COLOR_RGB(0, 0, 0);
EVE_CLEAR(1,1,1);
EVE_DISPLAY();
EVE_CMD_SWAP();
EVE_LIB_EndCoProList();
EVE_LIB_AwaitCoProEmpty();


    #if (defined EVE2_ENABLE || defined EVE3_ENABLE || defined EVE4_ENABLE)

// ---------------------- Reset all bitmap properties ------------------------
EVE_LIB_BeginCoProList();
EVE_CMD_DLSTART();
EVE_CLEAR_COLOR_RGB(0, 0, 0);
EVE_CLEAR(1,1,1);
for (i = 0; i < 16; i++)
{
EVE_BITMAP_HANDLE(i);
EVE_CMD_SETBITMAP(0,0,0,0);
}
EVE_DISPLAY();
EVE_CMD_SWAP();
EVE_LIB_EndCoProList();
EVE_LIB_AwaitCoProEmpty();
# else
   

    // ---------------------- Reset all bitmap properties ------------------------
EVE_LIB_BeginCoProList();
EVE_CMD_DLSTART();
EVE_CLEAR_COLOR_RGB(0, 0, 0);
EVE_CLEAR(1,1,1);
for (i = 0; i < 16; i++)
{
EVE_BITMAP_HANDLE(i);
//EVE_CMD_SETBITMAP(0,0,0,0);
        EVE_BITMAP_LAYOUT(0, 0, 0);
    EVE_BITMAP_SIZE(0, 0, 0, 0, 0);
}
EVE_DISPLAY();
EVE_CMD_SWAP();
EVE_LIB_EndCoProList();
EVE_LIB_AwaitCoProEmpty();
#endif
Best Regards, BRT Community

Hi,

Sorry, we have checked and there is an error in the datasheet, please find the corrections in red below.

The PCLK frequency in EXTSYNC mode can be calculated as:
PLL2 frequency = 12MHz * REG_PCLK_FREQ[9:4]
PCLK frequency = PLL2 frequency / REG_PCLK_FREQ[3:0] / 2
REG_PCLK_FREQ[11:10] is determined by PLL2 frequency range:
00: 20 – 40 MHz
01: 40 – 80 MHz
10: 80 – 160 MHz
11: 160 – 228 MHz

Note that the max PLL2 frequency is 228MHz and so the bits which set this must not be set such that the frequency exceeds this limit.

We are updating the datasheet to
- recommend using the values from the table written to the register instead of using the command to ensure that the values are calculated within limits (these should cover most cases and so can be used directly)
- and to correct this calculation.

Sorry for any inconvenience caused and we will have the document updated as soon as possible,

Best Regards, BRT Community

Hi,

Glad to hear it helped,

Yes, for EVE, you should set your display registers such that:

HOFFSET < (HCYCLE – HSIZE)
VOFFSET < (VCYCLE – VSIZE)

Without this, there can be cases where the swap wont succeed.

Instead of using the CMD_PCLK_FREQ we recommend to set the REG_PCLK_FREQ manually using the table 4-11 in the BT817 datasheet as these are the recommended values for each different PCLK frequency. We will be adding more guidance on this in the datasheet very soon,

Could you advise what your overall command list was to display the test card was?

Best Regards, BRT Community

Hello,

We are still in discussion with the R&D engineer regarding the oscillator/datasheet and will provide a response soon.

On your issue with the display, could you please tell me what display settings you have used for the display registers? The registers are as follows:

#define EVE_DISP_WIDTH 1024 // Active width of LCD display
#define EVE_DISP_HEIGHT 600 // Active height of LCD display
#define EVE_DISP_HCYCLE 1344 // Total number of clocks per line
#define EVE_DISP_HOFFSET 160 // Start of active line
#define EVE_DISP_HSYNC0 0 // Start of horizontal sync pulse
#define EVE_DISP_HSYNC1 100 // End of horizontal sync pulse
#define EVE_DISP_VCYCLE 635 // Total number of lines per screen
#define EVE_DISP_VOFFSET 23 // Start of active screen
#define EVE_DISP_VSYNC0 0 // Start of vertical sync pulse
#define EVE_DISP_VSYNC1 10 // End of vertical sync pulse
#define EVE_DISP_PCLK 1 // Pixel Clock
#define EVE_DISP_SWIZZLE 0 // Define RGB output pins
#define EVE_DISP_PCLKPOL 1 // Define active edge of PCLK
#define EVE_DISP_CSPREAD 0
#define EVE_DISP_DITHER 1

Best regards

BRT Community

Hello Mike,

I have passed on this information to an R&D engineer. I will let you know what they think is causing this issue.

Best regards

BRT Community

Hi Geethanjali,

Yes, as you mentioned Rudolph, there are a few steps needed to start-up EVE correctly including setting the clock settings (if you need them to be different from default) and then the active command followed by the read of REG_ID and awaiting the REG_CPU_RESET == 0;

There is a recommended start-up in the Programmers guide for whichever version of EVE which you use and also in the sample code and so you can use these for reference.

Here is an example waveform attached where we read the REG_ID. This is a BT816 in this case,

We take CS low to begin the transfer,
Then send the three byte address of REG_ID from the programmers guide with the most significant 2 bits as '0' which indicates to EVE that we are doing a read
Then send a dummy 0x00 byte (this only applies when doing a read)
And then a dummy 0x00 byte to get the result back. We are only interested in the data coming back on MISO
And finally, CS high again to end the transfer

Best Regards, BRT Community

Hello,

Thank you for your query.

The following link will take you to the BT81X Series Programming Guide: https://brtchip.com/wp-content/uploads/2021/09/BRT_AN_033_BT81X-Series-Programming-Guide.pdf.

In this guide, section 2 contains information on startup. Please take a look at section 2.4 in particular as it describes the initialization sequence during boot up.

If you need any more information please get in touch.

Best regards

BRT Community

Hi JuSil,

You can also put the image into flash with the EVE Screen Editor and so that might be worth trying

If it also gives the lines in ESE when you output to the module, could you send us a copy of the image and we can try it,

EVE4 also has a few features which can help to give more time for the display lines to be rendered. Please see page 51 of the Programmers guide:
https://brtchip.com/wp-content/uploads/Support/Documentation/Programming_Guides/ICs/EVE/BRT_AN_033_BT81X_Series_Programming_Guide.pdf

- Adaptive Frame rate varies the PCLK to allow more time for the screen to be rendered in cases where there are a lot of items to render. however, it is for RGB panels only and not all panels support it. Therefore, you could check this is off,

- REG_AH_HCYCLE_MAX is a new feature in BT817/8 which instead extends the HCYCLE value in cases where there are too many items to render in the time available (e.g. how much time one row has based on PCLK and number of pixels in a row). You could try this to see if allowing EVE to extend the HCYCLE time helps.

- There is also REG_UNDERRUN which allows you to check if the underrun is occurring and if so the REG_AH_HCYCLE_MAX may help.

If it works from RAM, it sounds like the image data being read from flash is slowing down the rendering. You could check that the BLOB is loaded and that the flash is in full speed mode. Also, if you try a lower quality conversion of the same image this may help to confirm if the issue is related to this.

For flash programming, please ensure that your module gets sufficient power from the USB adapter  as if the voltage to EVE or the flash droops, you get communication errors. Also, make sure all of the SPI cables are well connected and are as short as possible to avoid any signal quality issues.

Best Regards, BRT Community