Hi again

I keep have my problem and I realy don't know why... I am using the evaluation board for BT816, anything I do give me the same result..
As you can see below I have take off all my code driving the display ( who is working well)and made a code only for the sound..

Any thing i do in the register give me nothing.

   
    while (EVE_MemRead8(REG_ID)!= 0x7C);
     
    while (EVE_MemRead8(REG_CPURESET) != 0x00)                                  // Ensure CPUreset register reads 0 and so FT8xx is ready   
    {
    }
    delay_ms(5);
   
    EVE_MemWrite32(REG_FREQUENCY,60000000); // configuration de la l'horoge à 60 Mhz
    EVE_MemWrite16(REG_GPIOX_DIR, 0x0004);
    EVE_MemWrite16(REG_GPIOX, 0x0004); // bit 15 active le backlight
       
   delay_ms(500);
                                           
    EVE_MemWrite8(REG_VOL_SOUND, 0xFF);             
   EVE_MemWrite16(REG_SOUND,(0x6C<<8)|0x41);
    EVE_MemWrite8(REG_PLAY,1);
   
    while (EVE_MemRead8(REG_PLAY)!= 0);
   
      delay_ms(2000); 
I really be greatfull If someone could care of my problem and help me..

Best regard,

Hi Rudolph,

Thanks for your suggestion,

Yes we agree, it would be a very useful and convenient feature,

Our development team will add this in for a future release of EAB.

Best Regards, BRT Community

Hi everybody,

I am starting the development with the VM816 board, connected to a dspic, Actually all the display is working well, but I can't make any sound. and I don't understand why because it's look very easy.. I don't know why I always have a 30Mhz clock on the AUDIO_line output, even if I put the reg_sound to 0x0000 or 0x0060 for mute and set the REG_PLAY to 1
 Anything I put on the REG_sound give me this clock without modulation..

Do someone already had this problem ?

We are thinking to evaluate the BT816 for use with an 800x480 TFT panel. However calculations show issues with the required memory bandwidth for ATSC compressed images. Please correct me if some of the assumptions are wrong.

The FTDI is clocked at 72 MHz. Nominal dot clock for the panel is 40 MHz, maximum 50 MHz, so using the PCLK divider we run at 36MHz. From timing specs the horizontal raster time is 862-1200 dots (1056 nominal), giving 2112…2400 master clocks to build a scanline using the display list.

Now, from the datasheet and the ATSC 2×2 tile organization it is strongly inferred that the texture line cache size is 64 bytes: 2×2 ATSC blocks are 64 bytes, every address in flash must be multiple of 64 bytes and so on.

The fastest way to access the SPI flash is in quad SPI XIP mode, which is what the firmware blob I assume does… in this mode from the chip select the memory needs: 6 cycles for the address, 2 for the mode/address extension, 4 dummy cycles for access latency and then it outputs the data. So for a 64 byte transfer you need 44 master clocks.

Since a scanline runs for 2112…2400 clock you can only have 48-50 tile transfers in a line (for a 2×2 ATSC block tile). At the minimum compression level (4×4 texels for block) a tile represents 8×8 texels, so to hypotetically fill a full size background image (800 pixels) you would need 100 tiles and that doesn't fit the timings.

This is of course a bit extreme (since it's kind of a worse case, we could use bigger blocks and so on) but if there are many bitmaps (i.e. many characters) on the scanline, the texture unit/rasterize can definitely starve. What happen in this case? The condition is not described in neither the datasheet nor in the programming manual.

- The bitmap is not drawn? (like the old game console with something like max 5 sprites for scanline)
- The display list stalls? like when the display list is too long and there is no time to render all the pixels
- Something else?

On a smaller 480×272 panels there is a lot more time (because there are a) less pixels and b) dot clock is usually about 8MHz) so probably it isn't a concern, and I will try to lower the dot clock to see if it's feasible; this panel is currently running on the FT810 without issues however it seems to be quite sensible to the clock (for example it hangs if I try to do a snapshot) so I'd like to know what would actually happen if the scanline timing are exceeded due to memory accesses.

Thanks in advance
Regards

Hmm, push, just editing does not do anything to make this visible.

V5 is somewhat of a pre-release, I originally planned to release it following the release of BT817/BT818.
But things went very well and my optimisations had more effect than I anticipated.
I only removed everything I had implemented for BT817/BT818.

This is what it looks like to build the same small display list on a Cortex-M0+ with 48MHz:

V4
TFT_display() with DMA: 129µs
prog-size: 15436
TFT_display() without DMA: 360µs
prog-size: 15276

V5
TFT_display() with DMA: 51µs
prog-size: 12524
TFT_display() without DMA: 324µs
prog-size: 13420

And this is my example code running on an Arduino UNO clone with Mega328 and 16MHz.

V4:
TFT_display(): 664µs
prog-size: 12272

V5:
TFT_display(): 520µs
prog-size: 10322

Hello,

I succeeded, BT 816 START without problems.
I activated PWM DISPLAY, PCLK and GPIO after writing the first display list.
Now everything is OK, thanks for everything.

Best regards,


Sandu Onica

I am not sure what the actual issue is.
Well, okay, I get that you see the BT816 not starting reliably.
However, you also claim that you were using the FT800 and never had this issue.

The difference between FT80x and FT81x and beyond in regards of power down is that
you have to use the Power Down line with FT80x to wake it up.
And with FT81x and beyond it is possible to get from POWER DOWN state to ACTIVE state by SPI if EVE was brought
into POWER DOWN state by SPI and the PD_N pin is also high.

The price that you can wake up FT81x+ via SPI is a much higher "Power Down Current" since that internal voltage regulator can not be turned off.
That is not the issue, this is a feature and the remaining 0.2mA could be saved by switching off the power supply.

So your function to start a FT800 that you not had a problem with should be doing just fine starting a BT816.

My code always used the PD_N pin as a first measure in my EVE_init() und it is doing just fine with all EVEs.
Only for the case that the PD_N pin would not be connected for some reason I have this line in my EVE_init():
/* EVE_cmdWrite(EVE_CORERST,0); */ /* reset, only required for warm-start if PowerDown line is not used */

And I have it commented out since all my hardware connects the PD_N pin.

Hello,
Thank you for your advice.
I don't understand why 1 from 10 start up the touchscreen fails and another 9 times working good.

Best regards,

Sandu Onica

Hello,

It is possible that REG_CPURESET may not be 0 if the chip has not fully initialised.

If you assert and then deassert the PD line before the start-up sequence, it should reset the chip. Any change in the clock (CLK commands) should be done before the active command as these pout the device to sleep and the active (and the following delay of 300ms) must come after the clock commands.

When it fails to start, how far do you get through the recommended start-up process from section 2.4 of the programmers guide. did the REG_ID read 7C and the REG_CPURESET read 0?

Also, do you have all the new definitions for the registers of the BT816?

Best Regards,
BRT Community

4.9.3.4 POWERDOWN state
In POWERDOWN state, the clock oscillator, the PLL and the system clock applied to the BT815/6 core is disabled. The core engines are powered down while the SPI interface for host commands remains functional. All register contents are lost and reset to default when the chip is next switched on. The internal regulator remains on.

I POSTED FROM   BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0

Best regards,

SANDU ONICA