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Thank you for sharing your solution.


Best Regards,
BRT Community

Posting a followup in the hopes that it helps someone else in the future.  The root cause issue turned out to be an undocumented requirement with the FT811 that the REG_HCYCLE value must be greater than the sum of the REG_HOFFSET and REG_HSIZE values (same is true for the vertical timing).  I actually did have the ST7789 configured properly and running, but FT811 refused to perform the swap and draw a new screen unless the above condition was true.

For the actual ST7789 setup, I used a mux to share the CS between the display and the FT811, and this init code.  I configured the display as 4 line 8 bit serial II (IM[3:0] = 1110) which required another GPIO to toggle the D/CX line, but any serial config should work, with 9-bit 3 wire being the simplest.  Some of these delays are arbitrary and can likely be tightened up:

Set RESX low
50ms delay
set RESX high
50ms delay
set MADCTL to 0x00
set COLMOD to 0x66 (18-bit RGB mode)
send INVON command
set RAMCTRL to 0x11, 0xC2
set RGBCTRL to 0x40, 0x08, 0x14
send command DISPON
100ms delay
send command SLPOUT
100ms delay

For configruing the FT811:
// HORIZONTAL TIMING
#define hfp         38
#define hsw         10
#define hbp         10
#define h_active   240
#define h_total      (hfp + hsw + hbp + h_active+1) //+1 to make it actually swap

// VERTICAL TIMING
#define vfp         8
#define vsw         4
#define vbp         4
#define v_active   320
#define v_total      (vfp + vsw + vbp + v_active+1)  //+1 to make it actually swap
   
//Screen Settings
#define DISPLAY_HCYCLE      h_total            //total pixels/line
#define DISPLAY_HOFFSET      (hfp + hsw + hbp)   //(FP + sync width before active)
#define DISPLAY_HSYNC0      hfp               //(sync pulse starts after FP)
#define DISPLAY_HSYNC1      (hfp + hsw)         //(sync pulse ends)
#define DISPLAY_VCYCLE      v_total            //total lines/frame
#define DISPLAY_VOFFSET      (vfp + vsw + vbp)   //(FP + sync width before active)
#define DISPLAY_VSYNC0      vfp               //(sync pulse starts after FP)
#define DISPLAY_VSYNC1      (vfp+vsw)         //(sync pulse ends)   
#define DISPLAY_PCLK_POL   0               //rising edge output
#define DISPLAY_CSPREAD      1
#define DISPLAY_WIDTH      h_active
#define DISPLAY_HEIGHT      v_active
#define PCLK_DIV         3               //16Mhz when main clock set to 48MHz

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Thank you for joining our Bridgetek Webinar: "From Design to Device: Showcasing EVE Capabilities" held on 20 May 2026 at 3:00 PM (UK time).

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Update and a follow up now that I have actual hardware to work on:

I have been able to bring up the ST7789 based panel and draw some test screens to it over SPI to verify that the panel itself is configured properly and functions.

I can also verify that I can control the FT811, as I use it to toggle the DISP pin on the panel interface as well as control the backlight.

Unfortunately, I have not yet been able to have the FT811 drive the panel.  A simple output script results in no changes to the display:

Ft_Gpu_Hal_WrCmd32(CMD_DLSTART );
Ft_Gpu_Hal_WrCmd32(COLOR_RGB(35,144,255));
Ft_Gpu_Hal_WrCmd32(CLEAR(1,1,1));
Ft_Gpu_CoCmd_FgColor(COLOR_RGB(255,255,255));
Ft_Gpu_CoCmd_Text(24, 80, 29, OPT_CENTER, "Test");
Ft_Gpu_Hal_WrCmd32(DISPLAY());
Ft_Gpu_Hal_WrCmd32(CMD_SWAP );
Ft_Gpu_Hal_WaitCmdfifo_empty();
I seem to be missing some config option for the ST7789 to get it into RBG mode.  Screens written via the FT811 have no effect.  The previously linked code for ILI9488 doesn't fully apply to ST7789 as they are different ICs.   The ST7789 datasheet is not at all clear on what needs to be configured for RBG mode to work, only offering hints. 

Any suggestions?

Hi, I am still having this issue and it just made me publish my first youtube video ever.


Fortunately, while I had to rotate the display for my last project to landscape (EVE_cmd_setrotate(2) ), this was fine while EVE_cmd_setrotate(3; shows the same distortion.
Since the panel is IPS the viewing angle is the same from all sides anyways.

Thank you for joining our Bridgetek Webinar: "Designing Seamless Interfaces: Moving Beyond MCU Limitations," held on 15 April 2026 at 3:00 PM (UK time).

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For those who could not attend live, or if you'd like to revisit the content, the full webinar recording is now available as per below video.

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Come and register in our Next Webinar on 20 May 2026 @ 3pm UK time.

Bridgetek Webinar | From Design to Device – Showcasing EVE Capabilities

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