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Author Topic: FT81x and 800x600 screen resolution  (Read 11501 times)

yury_m

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FT81x and 800x600 screen resolution
« on: April 18, 2019, 01:59:26 PM »

Hi All,
I can not find correct display parameters for SVGA display (G084SN05V9).
The some screens on display has flickers and screen looks damaged.

Code: [Select]
FT_DispWidth = 800;
FT_DispHeight = 600;
FT_DispHCycle =  928;
FT_DispHOffset = 88;
FT_DispHSync0 = 0;
FT_DispHSync1 = 48;
FT_DispVCycle = 645;
FT_DispVOffset = 40;
FT_DispVSync0 = 0;
FT_DispVSync1 = 2;

Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_HCYCLE, FT_DispHCycle);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_HOFFSET, FT_DispHOffset);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_HSYNC0, FT_DispHSync0);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_HSYNC1, FT_DispHSync1);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_VCYCLE, FT_DispVCycle);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_VOFFSET, FT_DispVOffset);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_VSYNC0, FT_DispVSync0);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_VSYNC1, FT_DispVSync1);
Ft_Gpu_Hal_Wr8 (phost, (ft_uint32_t)REG_SWIZZLE, FT_DispSwizzle);
Ft_Gpu_Hal_Wr8 (phost, (ft_uint32_t)REG_PCLK_POL, FT_DispPCLKPol);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_HSIZE, FT_DispWidth);
Ft_Gpu_Hal_Wr16(phost, (ft_uint32_t)REG_VSIZE, FT_DispHeight);
Increasing Number of non-visible lines(FT_DispHOffset ,FT_DispVOffset) and total number of lines (FT_DispHCycle ,FT_DispVCycle ) can solve the problem on some of the screens but other screens still have flickers.
Where can i find optimal  parameters for display with that resolution?

Thank you
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Rudolph

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Re: FT81x and 800x600 screen resolution
« Reply #1 on: April 19, 2019, 08:45:42 AM »

The datasheet for the panel usually gives a few clues.
I have to admit though that translating the datasheet values into EVE parameters is a bit tricky.

Page 18 of the datasheet for the G084SN05V9 has timings.

FT_DispWidth = 800;
FT_DispHeight = 600;
FT_DispHCycle =  1056;
FT_DispVCycle = 628;

VSYNC0 and HSYNC0 are Zero for almost all displays with the exception for a few that are cut down from biiger panels.
Like a 3.8" that has been cut down from a 4.3".

FT_DispHSync0 = 0;
FT_DispVSync0 = 0;

REG_HOFFSET and REG_VOFFSET hold the length of the non-visiable parts and must be smaller
than xSIZE-xCYCLE.

FT_DispHOffset = 245;
FT_DispVOffset = 20;

Now these are tricky.
For EVE this is the horizontal front porch plus hsync pulse with and vertical front porch plus vsync pulse width.
The timing diagramm for the G084SN05V9 shows the blanking periods Tvb and Thb in front of the signals.
So I am guessing something like this could be working:

FT_DispVSync1 = 15;
FT_DispHSync1 = 200;


If anyone has more insight on this, a lecture on how this works would be welcome. :-)
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yury_m

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Re: FT81x and 800x600 screen resolution
« Reply #2 on: April 22, 2019, 08:12:25 AM »

Thank you for explanation.
It not solved the issue. At first tests all was according to datasheet and it did not work correctly on some screens. After i have started to play with values and found that increasing non-visible parts  makes outputs better but not at all screens. For example, if screen is not 'heavy' and have medium number of elements all work correctly. If screen have many elements (like keyboard panel with many buttons) - it starts to make problems. But increasing non-visible parts of the screen reduces FPS: frequency/(w*h).
I will try to change frequency, configuring timings is looks something magic
Next parameters looks good, but need make tests with more complex screens:
Clock is reduced to 30MHz
Code: [Select]
        FT_DispWidth = 800;
FT_DispHeight = 600;
FT_DispHCycle =  980;
FT_DispVCycle = 628;
FT_DispHSync0 = 0;
FT_DispVSync0 = 0;
FT_DispHOffset = 130;
FT_DispVOffset = 17;
FT_DispVSync1 = 15;
FT_DispHSync1 = 200;

But it is not exactly according to datasheet and i am afraid that problem is still not solved. It is strange that does not matter which values at VSync1 and HSync1, it is not affects on result. For example, VSync1=HSync1=2 looks same.
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BRT Community

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Re: FT81x and 800x600 screen resolution
« Reply #3 on: April 24, 2019, 10:42:38 AM »

The EVE series of ICs do not include a frame buffer, they dynamically clock out each computed pixel on the screen. A displays size and what the Pixel Clock is running at will determine the achievable performance.

If we take the example from the following WQVGA settings:
    // WQVGA display parameters
   lcdWidth   = 800;                                                            // Active width of LCD display
   lcdHeight  = 480;                                                            // Active height of LCD display
   lcdHcycle  = 928;                                                            // Total number of clocks per line
   lcdHoffset = 88;                                                             // Start of active line
   lcdHsync0  = 0;                                                               // Start of horizontal sync pulse
   lcdHsync1  = 48;                                                            // End of horizontal sync pulse
   lcdVcycle  = 525;                                                           // Total number of lines per screen
   lcdVoffset = 32;                                                            // Start of active screen
   lcdVsync0  = 0;                                                              // Start of vertical sync pulse
   lcdVsync1  = 3;                                                              // End of vertical sync pulse
   lcdPclk    = 2;                                                                  // Pixel Clock
   lcdSwizzle = 0;                                                              // Define RGB output pins
   lcdPclkpol = 1;                                                              // Define active edge of PCLK
                   

HCYCLE = 928
VCYCLE = 525
VCYCLE * HCYCLE  = 487,200

Note: REG_PCLK is using the value 2 which will divide PCLK down to 30Mhz.

Result = 30,000,000/487,200 = ~ 61 fps
 
 
If there are too many elements (display list items which intersect a given point) to compute for a pixel, this is when you will see corruption. Which is why reducing the PLCK (and thus the frame rate) will remove some errors, essentially you are giving EVE more time to compute what should be on a given line. I would suggest dividing PCLK down further to see if this improves the results.
 
Our new BT81X has a feature that will vary the PLCK allowing for more computational elements if the screen supports this. What EVE IC are you using?
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yury_m

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Re: FT81x and 800x600 screen resolution
« Reply #4 on: April 24, 2019, 01:02:02 PM »

Hi,
FT810Q EVE is used.
Datasheet of the LCD (G084SN05 V9) says that 30MHz is a minimum working clock. Reducing the PLCK cause to completely non working LCD. But if i reduce pixel clock to 30MHz (lcdPclk=2)  - EVE computations will be reduced too according to the new lower clock? And will not be more time on computations. Or system clock (EVE) stays 60MHz and only pixel clock is changed and system clock is not same as pixel clock and Pclk divider applies only for pixel clock? If yes, i can increase system clock and reduce more pixel clock with lcdPclk.
All screens are not ready yet and i do not know if problem will back. Because of that i would like to know optimal characteristics for 800x600 LCD with 30MHz pixel clock. All EVE examples are for displays up to 800x480 and no one for 800x600. For example, documentation says that VOFFSET hold the length of the non-visible parts and must be smaller than VCYCLE -VSIZE, but how many smaller? At the other side, I understand that all timings are specific for each LCD and not common one.
Thank you
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BRT Community

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Re: FT81x and 800x600 screen resolution
« Reply #5 on: April 26, 2019, 02:34:12 PM »

Hello,

Reducing the PCLK allows more computational time per pixel for EVE as it dynamically clocks out a given screen. Thus reducing the PCLK can improve performance for computationally heavy screens.

The system clock and the pixel clock are not the same, the pixel clock is derived from the system clock using pixel clock divider, REG_PCLK.

The only stipulation for VOFFSET is that it is  smaller than (VCYCLE -VSIZE).

Best Regards,
BRT Community
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