Hello,
Thanks for the update, I'm glad you have managed to display the image now.
As per table 4-11 in the datasheet 0xd12 should equate to 51Mhz on for the PCLK frequency:
https://brtchip.com/wp-content/uploads/Support/Documentation/Datasheets/ICs/EVE/DS_BT817_8.pdfI would also recommend setting REG_HCYCLE to the value noted in your displays datasheet, as the display is has a width of 600 the HCYCLE value should be close to this number as this denotes the number of Horizontal scan out lines EVE has to process.
The EVE series of ICs do not include a frame buffer, they dynamically clock out each computed pixel on the screen for every screen refresh. A displays size and what the Pixel Clock is running at will determine the achievable performance, and conversely how long EVE has to pull any graphic asset data from an attached flash IC.
If we take the following example from the following WQVGA settings for working out a displays frame rate i can explain what has happened (note: this is an FT81x example but the princile still applies):
// WQVGA display parameters
lcdWidth = 800; // Active width of LCD display
lcdHeight = 480; // Active height of LCD display
lcdHcycle = 928; // Total number of clocks per line
lcdHoffset = 88; // Start of active line
lcdHsync0 = 0; // Start of horizontal sync pulse
lcdHsync1 = 48; // End of horizontal sync pulse
lcdVcycle = 525; // Total number of lines per screen
lcdVoffset = 32; // Start of active screen
lcdVsync0 = 0; // Start of vertical sync pulse
lcdVsync1 = 3; // End of vertical sync pulse
lcdPclk = 2; // Pixel Clock
lcdSwizzle = 0; // Define RGB output pins
lcdPclkpol = 1; // Define active edge of PCLK
HCYCLE = 928
VCYCLE = 525
VCYCLE * HCYCLE = 487,200
Note: REG_PCLK is using the value 2 which will divide PCLK down to 30Mhz.
Result = 30,000,000/487,200 = ~ 61 fps
From the above example we can see that the pixel clock and the display settings affect the refresh rate, again the slower a screen refresh rate the longer EVE has to process any data to draw the screen or pull data from an attached flash IC.
In your case it would appear that you maintained the EVE_DISP_PCLK_FREQ (PLCK frequency) setting and are clocking the display at 2.55Mhz where REG_PLCK = 20 (Note: you may want to check your displays datasheet to check the applicable range for its pixel clock). You have also set REG_HCYCLE to 2000, this along with slowing the pixel clock has the effect that it will slow down the displays refresh rate, thus allowing more time for EVE and the SPI interface to pull the image data from flash and construct the screen for the given screen refresh.
Again, i would suggest resetting REG_HCYCLE to your display recommended value, you can then play with the pixel clock (via EVE_DISP_PCLK_FREQ and EVE_DISP_PCLK) until you are not experiencing underrun whilst loading the image from flash.
Best Regards,
BRT Community