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[Maxzillian]

I'm having trouble getting dual SPI mode to work. I've got some test code stood up that first reads REG_SPI_WIDTH which returns 0 as expected. I then try to set bit 0 to 1 using a write command, but this does not seem to take. I've verified this two ways:

* Read REG_SPI_WIDTH again to see if the new setting is in effect (this always returns 0) reading in both normal and dual SPI modes
* Read chip ID to see if it can be read back. No matter what I get the correct ID reading it in normal mode which suggests the setting has not taken effect

When exactly does the change take effect? I assume after CS is released? Does this register need to be handled as 32 bits or 8 bits? What is the correct offset for REG_SPI_WIDTH? 0x188?

The following code example is for the ESP-IDF.

Code: [Select]

#define REG_SPI_WIDTH        0x00302188
#define MEM_WRITE 0x80

static const uint8_t rxBits = 32;
trans.addr = REG_SPI_WIDTH;
trans.length = 0;
trans.rxlength = rxBits + dummyBits; //default to same as length
trans.tx_buffer = NULL;
trans.rx_buffer = rxBuf;
ret = spi_device_polling_transmit(EVE_spi_device, &trans);
assert(ret==ESP_OK);

uint32_t regSPI = 0;
memcpy(&regSPI, rxBuf+1, 4);
printf("%x\n", regSPI);

// write new register value, I've considered MSB and LSB encoding for these with no observed differences
trans.tx_data[0] = 0x1;
trans.tx_data[1] = 0x0;
trans.tx_data[2] = 0x0;
trans.tx_data[3] = 0x0;

trans.addr = REG_SPI_WIDTH | (MEM_WRITE << 16);
trans.length = rxBits;
trans.rxlength = 0;
trans.tx_buffer = NULL;
trans.rx_buffer = NULL;
trans.flags = SPI_TRANS_USE_TXDATA;
ret = spi_device_polling_transmit(EVE_spi_device, &trans);
assert(ret==ESP_OK);

trans.addr = REG_SPI_WIDTH;
trans.length = 0;
trans.rxlength = rxBits + dummyBits;
trans.tx_buffer = NULL;
trans.rx_buffer = rxBuf;
trans.flags = 0;
//trans.flags = SPI_TRANS_MODE_DIO;
ret = spi_device_polling_transmit(EVE_spi_device, &trans);
assert(ret==ESP_OK);

memcpy(&regSPI, rxBuf+1, 4);
printf("%x\n", regSPI);

This is occurring after initialization and after fast flash has been enabled.

Edit: I did another test where I switched to dual SPI shortly after the check of REG_CPU_RESET during initialization and this seems to have worked. Is it not possible to switch SPI modes at some point?

[Maxzillian]

With some further testing I can check off a few questions:

*The offset of REG_SPI_WIDTH is 0x188 (the programming manual (v2.1) incorrectly states it is 0x180)
*You can write to the register using just 8 bits despite the manual indicating it's a 32 bit register
*This does appear to take effect once CS is released

So I really only have one outstanding question which is whether or not the SPI mode can be switched from normal to dual/quad at any time or if there is only a certain window during which this can take place.