FT81x with ST7789V

[ashrey]

I found this thread, which is quite old and suggests making a new thread, so I did:
http://www.brtcommunity.com/index.php?topic=220.0

There also weren't any definitive answers in that thread, and I amhoping that has changed since it was posted.

I have previously used a FT810 with a natively RGB panel, and am now looking at using a FT811 (48pin) with this panel that has a ST7789V controller on it: https://www.buydisplay.com/2-4-inch-ips-240x320-tft-lcd-display-capacitive-touch-screen

I think I have  the connections correct, and am looking for confirmation:
Panel    FT811
VSYNC    VSYNC
HSYNC    HSYNC
DOTCLK  PCLK
DE      DE
DB17:0  R7:2|G7:2|B7:2
RESET    DISP

The RD, WRX, D/CX, CSX, and TE pins from the panel are all unused

As the other thread asks, it also appears that the ST7789V needs to be configured via SPI before it will work in RGB mode, but then after that, SPI communications to the display are no longer needed, is that correct?

My current design already has several devices on the SPI bus and can't natively support another CS, but if the ST7789V only requires a few SPI instructions for initialization, I can can easily MUX the FT811 CS and use an MCU GPIO to control whether SPI traffic selects the ST7789V or the FT811.

Thanks

[BRT Community]

Hello,

Thank you for your post.

As the other thread asks, it also appears that the ST7789V needs to be configured via SPI before it will work in RGB mode, but then after that, SPI communications to the display are no longer needed, is that correct?

Yes, generally this is correct for such parts (but please verify the in the datasheet) that you would configure the display driver during boot, and once this ahs been completed you wouldn't communicate with it again. After which you can perform the FT81x initialization routine.

For reference, here is some example code that would be called for the ILI9488 configuration on the ME810A-HV35R:
https://github.com/Bridgetek/EveApps/blob/master/common/eve_hal/EVE_ILI9488_FT9XX.c

In regards to the configuration of parts such as the ST7789V, there are two approach's you can utilise.

• The first approach would be to utilise the SPI interface on your MCU to perform the configuration, using a spare CS# signal.

As noted in the previous thread you can get an example of the hardware we use in the ME810A-HV35R datasheet.

But it would also be acceptable to use the approach you has suggested to MUX the CS# line to the ST7789V and the FT811 and control this via a GPIO.

• The second approach would be to bit bang the configuration data from your MCU over spare GPIO pins if you have these available.

This would remove the need for the MUX IC if you have some spare GPIO pins available.


Best Regards,
BRT Community

[ashrey]

Update and a follow up now that I have actual hardware to work on:

I have been able to bring up the ST7789 based panel and draw some test screens to it over SPI to verify that the panel itself is configured properly and functions.

I can also verify that I can control the FT811, as I use it to toggle the DISP pin on the panel interface as well as control the backlight.

Unfortunately, I have not yet been able to have the FT811 drive the panel.  A simple output script results in no changes to the display:

Code Select Expand

Ft_Gpu_Hal_WrCmd32(CMD_DLSTART );
Ft_Gpu_Hal_WrCmd32(COLOR_RGB(35,144,255));
Ft_Gpu_Hal_WrCmd32(CLEAR(1,1,1));
Ft_Gpu_CoCmd_FgColor(COLOR_RGB(255,255,255));
Ft_Gpu_CoCmd_Text(24, 80, 29, OPT_CENTER, "Test");
Ft_Gpu_Hal_WrCmd32(DISPLAY());
Ft_Gpu_Hal_WrCmd32(CMD_SWAP );
Ft_Gpu_Hal_WaitCmdfifo_empty();
I seem to be missing some config option for the ST7789 to get it into RBG mode.  Screens written via the FT811 have no effect.  The previously linked code for ILI9488 doesn't fully apply to ST7789 as they are different ICs.   The ST7789 datasheet is not at all clear on what needs to be configured for RBG mode to work, only offering hints. 

Any suggestions?

[ashrey]

Posting a followup in the hopes that it helps someone else in the future.  The root cause issue turned out to be an undocumented requirement with the FT811 that the REG_HCYCLE value must be greater than the sum of the REG_HOFFSET and REG_HSIZE values (same is true for the vertical timing).  I actually did have the ST7789 configured properly and running, but FT811 refused to perform the swap and draw a new screen unless the above condition was true.

For the actual ST7789 setup, I used a mux to share the CS between the display and the FT811, and this init code.  I configured the display as 4 line 8 bit serial II (IM[3:0] = 1110) which required another GPIO to toggle the D/CX line, but any serial config should work, with 9-bit 3 wire being the simplest.  Some of these delays are arbitrary and can likely be tightened up:

Set RESX low
50ms delay
set RESX high
50ms delay
set MADCTL to 0x00
set COLMOD to 0x66 (18-bit RGB mode)
send INVON command
set RAMCTRL to 0x11, 0xC2
set RGBCTRL to 0x40, 0x08, 0x14
send command DISPON
100ms delay
send command SLPOUT
100ms delay

For configruing the FT811:
// HORIZONTAL TIMING
#define hfp         38
#define hsw         10
#define hbp         10
#define h_active   240
#define h_total      (hfp + hsw + hbp + h_active+1) //+1 to make it actually swap

// VERTICAL TIMING
#define vfp         8
#define vsw         4
#define vbp         4
#define v_active   320
#define v_total      (vfp + vsw + vbp + v_active+1)  //+1 to make it actually swap
   
//Screen Settings
#define DISPLAY_HCYCLE      h_total            //total pixels/line
#define DISPLAY_HOFFSET      (hfp + hsw + hbp)   //(FP + sync width before active)
#define DISPLAY_HSYNC0      hfp               //(sync pulse starts after FP)
#define DISPLAY_HSYNC1      (hfp + hsw)         //(sync pulse ends)
#define DISPLAY_VCYCLE      v_total            //total lines/frame
#define DISPLAY_VOFFSET      (vfp + vsw + vbp)   //(FP + sync width before active)
#define DISPLAY_VSYNC0      vfp               //(sync pulse starts after FP)
#define DISPLAY_VSYNC1      (vfp+vsw)         //(sync pulse ends)   
#define DISPLAY_PCLK_POL   0               //rising edge output
#define DISPLAY_CSPREAD      1
#define DISPLAY_WIDTH      h_active
#define DISPLAY_HEIGHT      v_active
#define PCLK_DIV         3               //16Mhz when main clock set to 48MHz

[BRT Community Admin]

Thank you for sharing your solution.


Best Regards,
BRT Community