News:

Welcome to the Bridgetek Community!

Please read our Welcome Note

Technical Support enquires
please contact the team
@ Bridgetek Support

Please refer to our website for detailed information on all our products - Bridgetek - Bridging Technology

Main Menu

Errata in examples for FT90x

Started by scoprioprise, February 20, 2019, 01:46:57 PM

Previous topic - Next topic

scoprioprise

I just wanted to sum up errors ( or, at least, not so clear statements ) in code examples.
By now, I found:


  • CAN example 3: tx.data[] is a 8 byte array, so you can't access the tx.data[8] element. In other languages, you would get an OutOfBoundException, here you read/write spurious data. Not a big deal, however can lead to strange behaviour in other codes.
  • DAC example 1: dac_start(0) with dac_mode_single starts the FIFO mechanism, thus leading to a delay in first output and a buffer delay when passing "realtime" data. DAC_write starts the dac itself, so there's no need (not to say, erroneous)  to explicitly start the DAC.


Hope you all can add your experience, thus helping refining documentation.

BRT Community

Hello Filippo,

The 2nd bullet point was already confirmed by us.

Let us look into the first point.

If there are any code errors, we will update in the next toolchain release.

In any case, the source code is provided so you can make any changes.

Best Regards,
BRT Community