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Author Topic: FT812 Quad SPI interface  (Read 8652 times)

Goran

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FT812 Quad SPI interface
« on: March 12, 2021, 09:54:30 AM »
I have a NXP uC connected by quad SPI to the FT812 chip. When running at full speed in quad mode I get problems with reading data from the Ft chip.
The first 2 bytes read back after sending address is just repetition of last 4bits of the address. I've tried different drive strengths(both command wise and GPIOX reg) settings and dummy byte settings without success.

(That's also an interesting thing where it in sample code for the FT81x is used two dummy bytes in quad mode without explanation in data sheet or program manual. Why is that?)

At lower speed, aprox 16MHz I get correct output data, at speeds in between it is a mix of faulty and correct readings. Is there any known explanation to this or ways to handle it?
Is there any errata sheet for the FT812?

Best Regards
Goran
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Re: FT812 Quad SPI interface
« Reply #1 on: March 12, 2021, 04:09:57 PM »
Hello Goran,

Thank you for your question.

The extra dummy byte when in quad mode is to allow for turn around time. Bit 2 of the REG_SPI_WIDTH register controls this: "Extra dummy on SPI read transfer. Writing 1 to enable one extra dummy byte on SPI read transfer." Have you configured this register in your application? I would suggest matching your low level SPI code to match this registers setting.

Would you be able to provide some logic analyser captures of the SPI lines when running at 16MHz and 'full speed'?
I note you have adjusted the drive strength on your SPI lines, have you tried altering slew rate also?

There are no current errata's for the FT812.

Best Regards,
BRT Community
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Goran

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Re: FT812 Quad SPI interface
« Reply #2 on: March 17, 2021, 02:56:01 PM »
Hi,

Thanks for your reply, With help from your comments I’ve found the problem and sorted it out.
It was about the extra dummy byte, which i thought I had implemented but in reality not.

Not having the same microcontroller as in your example code I had to rewrite the low level routines. Therefor copying a part of the ”Gpu_Hal_SetSPI” function. Looking deeper into that example code it seems it has double faults that normally takes each other out. (Mixing up bus width and number of dummy bytes) But when I took half of it (the dummy byte part) got a single fault.

Best Regards,
Goran
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Re: FT812 Quad SPI interface
« Reply #3 on: March 17, 2021, 03:40:11 PM »
Hello Goran,

Glad to hear you have resolved the issue!
Please let us know if you have any further questions.

Best Regards,
BRT Community
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