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Author Topic: BT818 PCLK settings  (Read 3467 times)

Rudolph

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Re: BT818 PCLK settings
« Reply #15 on: October 12, 2021, 04:46:54 PM »

Quote
We are updating the datasheet to
- recommend using the values from the table written to the register instead of using the command to ensure that the values are calculated within limits (these should cover most cases and so can be used directly)

This makes me curious and I may need to re-check my results but as far as I can tell CMD_PCLKFREQ is working just fine.
With a crystal or resonator CMD_PCLKFREQ is setting up the display-clock correctly and over a wide range as well.
I did an experiment a while ago for which I gradually slowed the pixel clock and the resulting frames per second calculated using REG_FRAMES always was very close to the expected value.

There is an issue with the internal oscillator and now I am wondering if the oscillator is running at only 6MHz instead of 12MHz or if CMD_PCLKFREQ somehow messes up the configuration when the internal oscillator is active.
But then, the internal oscillator is not an valid option for the BT81x anymore anyways since it was removed from the datasheet.
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durian

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Re: BT818 PCLK settings
« Reply #16 on: October 12, 2021, 06:34:23 PM »

Thanks, I've updated my code to calculate REG_PCLK_FREQ according to the new instructions instead of using CMD_PCLKFREQ.

I still have to calculate the values based on twice my desired PCLK frequency, but perhaps that is because I'm using the internal clock and not the external oscillator.

Can you please comment on the HOFFSET < (HCYCLE - HSIZE) constraint based on my example above. I can't see how it is possible to meet that constraint when you are using VESA timings or timings provided by the display over DDC. When using those timings, HOFFSET = (HCYCLE - HSIZE). HOFFSET is the sum of all blanking pixels and HSIZE is the active pixels. In order for HCYCLE > HOFFSET + HSIZE, there would need to be extra PCLK cycles not assigned to either active or blanking pixels. If you were to arbitrarily increase HCYCLE to more than HOFFSET + HSIZE, you would also need a PCLK frequency higher than the one in the VESA timings.

I did experiment with increasing HCYCLE and leaving HOFFSET and HSIZE as-is, but the display didn't like it. It had a difficult time syncing.

Thanks,
mike
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BRT Community

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Re: BT818 PCLK settings
« Reply #17 on: October 27, 2021, 04:58:48 PM »

Hi,

On many TFT displays a range of values are permitted allowing some flexibility, if yours are different could you advise what screen you are using and a bit more information on it?

Best regards

BRT Community
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durian

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Re: BT818 PCLK settings
« Reply #18 on: October 27, 2021, 05:14:10 PM »

It's not a specific screen. The display is connected via HDMI. We either use timings provided by the display over HDMI DDC or by using standardized VESA timings.

I thought the BT81x did its scan line rendering during the blanking period (hoffset). If so, why does it need hcycle to be larger than the active (hsize) + blanking (hoffset) periods?

If those extra cycles are indeed required for some purpose, how much time is required? Is it a duration (a certain number of milliseconds or microseconds) or a number of pixel clocks?

mike
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BRT Community

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Re: BT818 PCLK settings
« Reply #19 on: November 01, 2021, 02:38:41 PM »

Hi,

If you provide the display resolution, we can recommend register settings. Otherwise, please point out which VESA setting is not working.

For HDMI displays, there must be a RGB to HDMI bridge chip between BT818 and HDMI connector. Please make sure the HDMI chip is properly configured.

Best regards

BRT Community
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durian

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Re: BT818 PCLK settings
« Reply #20 on: November 01, 2021, 05:40:34 PM »

Yes, I have a bridge chip for the HDMI interface. I use a TFP420.

As an example, here is the VESA timing for 640x480 @60MHz:

pixel clock = 25175000
horizontal active pixels = 640
horizontal blank = 160
horizontal front porch = 16
horizontal sync = 96
vertical active lines = 480
vertical blank = 45
vertical front porch = 10
vertical sync = 2

Given this timing, I set the BT818 registers as follows:
HCYCLE = 800
HSIZE = 640
HOFFSET = 160
HSYNC0 = 16
HSYNC1 = 112
VCYCLE = 525
VSIZE = 480
VOFFSET = 45
VSYNC0 = 10
VSYNC1 = 12

I can get output using these timing values (and PCLK twice as fast as required and CSPREAD disabled), but I want to be able to handle general cases as well - where timing information is extracted from the display using DDC and it is not known in advance. Here are my questions:

1) Does the BT818 render each line during the blanking period (HOFFSET)?
2) Why does HCYCLE need to be greater than HSIZE + HOFFSET, instead of greater than or equal to HSIZE + HOFFSET? I don't see any cycles in the Figure 4-6 RGB Timing Waveforms from the datasheet that would allow HOFFSET < HCYCLE - HSIZE.
3) Is the blanking period (HOFFSET) not sufficient for rendering?
4) If it is not sufficient, how do I calculate how much addition time is required?
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BRT Community

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Re: BT818 PCLK settings
« Reply #21 on: November 04, 2021, 09:55:47 AM »

Hi,

To convert VESA timing to EVE RGB registers, you can refer to BT817/8 Datasheet page 26 Table 4-14 and fig 4-6 https://brtchip.com/wp-content/uploads/Support/Documentation/Datasheets/ICs/EVE/DS_BT817_8.pdf; or AN_336 page 6-7 https://brtchip.com/wp-content/uploads/Support/Documentation/Application_Notes/ICs/EVE/AN_336_FT8xx-Selecting-an-LCD-Display.pdf.

CYCLE = active + blank
SIZE = active
OFFSET = sync + back porch ( = blank - front porch)
SYNC0 = 0
SYNC1 = sync

For the given VESA timing for 640x480@60Hz, the recommended BT818 register values are:
HCYCLE = 800
HSIZE = 640
HOFFSET = 144
HSYNC0 = 0
HSYNC1 = 96
VCYCLE = 525
VSIZE = 480
VOFFSET = 35
VSYNC0 = 0
VSYNC1 = 2

PCLK = 1
PCLK_FREQ = 0x0D14 (the closed pixel frequency that BT818 can supply is 25.5MHz)
PCLK_POL = 0 or 1, depend on the HDMI chip clock porality.

1) Does the BT818 render each line during the blanking period (HOFFSET)?

Valid RGB data will start to clock out after HOFFSET, indicated by DE going to active.

2) Why does HCYCLE need to be greater than HSIZE + HOFFSET, instead of greater than or equal to HSIZE + HOFFSET? I don't see any cycles in the Figure 4-6 RGB Timing Waveforms from the datasheet that would allow HOFFSET < HCYCLE - HSIZE.

HOFFSET is not the whole blanking period. It includes sync and back porch, and may include part of the front porch(HSYNC0) . Datasheet Table 4-14 has provided requirements that HOFFSET must be < HCYCLE – HSIZE.

3) Is the blanking period (HOFFSET) not sufficient for rendering?

BT818 scanout does not depend on blanking. The blanking is required by the display panel.

4) If it is not sufficient, how do I calculate how much addition time is required?

Blanking timing is provided by display panel. If the display panel allows a range of blanking period, it is recommended to set BT818 total blanking to the maximum allowed by the display panel, thus more line time for graphics processing.

Best regards

BRT Community
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durian

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Re: BT818 PCLK settings
« Reply #22 on: November 04, 2021, 05:18:20 PM »

Thank you. AN_336 helps. It says that HOFFSET should be Back Porch + Sync Pulse + (Front Porch - X), where X >= 1. This also applies to SYNC0 and SYNC1. Where ever you see the Front Porch, you should use (Front Porch - X). Table 3.1 and Figure 3.2 show this.

I was using the BT817_8 datasheet (version 1.1 - the same as the one you link to). It is different. Table 4-14 from the datasheet is similar to Table 3.1 in the app note, but does not say to reduce the front porch. The Display Parameter column of Table 4-14 says HOFFSET = Front Porch + Sync Pulse + Back Porch. The Front Porch is used without being reduced. The verbiage in the Description column says HOFFSET < HCYCLE - HSIZE, but that does not agree with what is shown in the Display Parameter column.

This discrepancy is also seen in Figure 4-6. Figure 4-6 is similar to the app note's Figure 3.2. However, the figure in the app note shows a reduced value for the Front Porch. The figure in the datasheet shows the full duration of the Front Porch.

Based on what you are saying, the app note is correct and the datasheet should be corrected.

The app note says X (the value used to reduce the front porch) must be >= 1. Is there any further restriction on this or is it always acceptable to use X=1?

Thank you for the clarification,
mike
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moiatto

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Re: BT818 PCLK settings
« Reply #23 on: November 29, 2021, 05:26:41 PM »

I gave up .... after 3 days of trying to get the monkey out of the hat with all my knowledge  :(

Until now, I was very happy to use a VM816C50A evaluation board with TFT IPS 5" 800x480. All worked fine...animation, images, all stored in flash. All assets created with old EAB v2.1.0. Perfect with ESP32 and Teensy 4.0 boards.

3 days ago I got a Riverdi RVT70HSBNWC00-B, 7.0" IPS 1024x600 with BT817.

So, I update my library to work with new BT817/8 (I sped up thanks to Rudolph's library. Thanks Rudolph! I'm old school. I use the basic Arduino IDE, No VS IDE, No PlatformIO).

After reading this thread, I initialize the registers of BT817 board in the library with the Riverdi datasheet:
Quote
REG_HSIZE          1024
REG_VSIZE          600
REG_HCYCLE       1344
REG_HOFFSET     160
REG_HSYNC0       0
REG_HSYNC1       70
REG_VCYCLE        635
REG_VOFFSET      23
REG_VSYNC0        0
REG_VSYNC1        10
REG_PCLK             1
REG_SWIZZLE       0
REG_PCLK_POL      1
REG_CSPREAD       0
REG_DITHER         0
REG_PCLK_FREQ    0xD12   // 51 MHz
REG_PCLK_2X        0

See attached Riverdi TFT RGB timing characteristics.

No SPI communication problems with ESP32 and Teensy 4.0 cards.
The BT817 responds well. Problem-free initialization.
Set Flash mode in full speed OK.

set REG_FREQUENCY = 72MHz.
I directly set REG_PCLK_FREQ as suggest here instead of use cmd_pclkfreq. The data read was the same as the set.

The problems start now:

***** with REG_PCLK_FREQ  = 0xD12 (51 MHz) (Riverdi setting) ********
1. Primitives and Widgets work correctly...OK
2. cmd_testcard() show the testcard graphic but with flickering
3. Images and animations from Flash....NOTHING (when try image I see white screen instead with animation black screen)

***** with REG_PCLK_FREQ  = 0x451 (30 MHz) ********
1. Primitives and Widgets work correctly...OK
2. cmd_testcard() show the testcard graphic but with flickering
3. Images and animations from Flash...I can see single small images, if more then two / three, it makes a mess up with flickering, same for the animation. Only small animation (size 150x150 px). otherwise it make a mess up.

***** with REG_PCLK_FREQ  = 0x883 (16 MHz) This one is the least worst ********
1. Primitives and Widgets work correctly... but with flickering
2. cmd_testcard() show the testcard graphic but with flickering
3. Images and animations from Flash....same as 0x451 (30 MHz) but I can distinguish something with wrong colors.

***** with REG_PCLK_FREQ  = 0x891 (54 MHz) ********
1. Primitives and Widgets work correctly...OK
2. cmd_testcard() show the testcard graphic but with flickering
3. Images and animations from Flash....I can see small images sometimes but animation nothing, only many horizontal lines moving downwards

***** with REG_PCLK_FREQ  = 0x891 (60 MHz) default setting ********
1. Primitives and Widgets work correctly...OK
2. cmd_testcard() show the testcard graphic but with flickering
3. Images and animations from Flash....white screen with flickering

***** with REG_PCLK_FREQ  = 0x8C1 (72 MHz) default setting ********
1. Primitives and Widgets work correctly...OK
2. cmd_testcard() show the testcard graphic but with flickering
3. Images and animations from Flash....white screen with flickering


I don't know what other tests I can do anymore  :'(
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Rudolph

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Re: BT818 PCLK settings
« Reply #24 on: December 02, 2021, 09:00:13 PM »

I do not only have the EVE_RVT70H profile in EVE_config.h , I do have one on my desk right now and it works just fine with this profile.
The "5.x" branch has this as "untested" but the "5_plus" branch has this updated to "/* tested with RVT70HSBNWC00-B */".

I am still using EVE_cmd_pclkfreq() since I have no issue at all with it and there was no explanation whatever issue there might be.

I did encounter a hardware issue with the Teensy 4.1 though, I had to increase the series resistor for the SPI lines between the Teensy and my display adapter board.
One of these boards: https://github.com/RudolphRiedel/EVE_display-adapter/tree/master/L-D5019-01-05
I am not sure what the issue is but every other controller I worked with had no issue.

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moiatto

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Re: BT818 PCLK settings
« Reply #25 on: December 07, 2021, 03:34:20 PM »

Hi Rudolph,
thanks for your reply.

I have only one slave device connected on SPI bus, the Rivendi TFT without shift levels, because teensy 4.0 works already at 3V3.
I don't use resistors but direct connections. Correct?

With teensy 4.0 board, I init the EVE3/EVE4 with spi bus speed at 12MHz, after it works at 30MHz (with VM816C board works very fine).

After I bit of work on my library, I have resolved some issues with EVE4 chips.

cmd_testcard() works fine now. widgets and primitives too.

Now my problem is with assets stored on flash ram. Expecially with animation frame cmd_animframe().

The assets (images all ASTC 4x4 and animations all ASTC 4x4) on VM816 board work perfectly, but the same assets with BT817 don't work correctly.

I have noticed that with big size images (approximately more then 700x250) and with big size animation (approximately 800x250 for example), the BT817 show white screen or 3 half images of the same frame for example.

I don't understand where the problem is.
The flash state is correctly set in full mode.

What can I try to do?

For last, I have modified your library to work with Arduino IDE and it reports the same issues.
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moiatto

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Re: BT818 PCLK settings
« Reply #26 on: December 17, 2021, 07:34:14 PM »

Which crystal oscillator do you use or recommend for new custom EVE3 or EVE4 boards? make and model.
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BRT Community

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Re: BT818 PCLK settings
« Reply #27 on: December 20, 2021, 11:35:22 AM »

Hello,

On our development boards we utilize the Abracon LLC - "ABM8G-12.000MHZ-18-D2Y-T" 12Mhz 18pF crystal.

Best Regards,
BRT Community
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Rudolph

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Re: BT818 PCLK settings
« Reply #28 on: December 20, 2021, 01:53:25 PM »

>What can I try to do?

I have no real hands-on experience with the animation feature.

>For last, I have modified your library to work with Arduino IDE and it reports the same issues.

What did you modify?

I admit that I am done now with the Arduino "IDE" and strongly suggest to use PlatformIO with VSCode instead to compile for Arduino.

But to make the example compile with the Arduino IDE I just downloaded 1.8.18.
Then I took https://github.com/RudolphRiedel/FT800-FT813/tree/5.x/examples/EVE_Test_Arduino_PlatformIO/src
Renamed the folder to EVE_Test, renamed EVE_Test.cpp to EVE_Test.ino and copied all the .c, .h and .cpp from https://github.com/RudolphRiedel/FT800-FT813 to this folder.

And this fails in EVE_config.h as there is no define for the display.
As I could not find an option in the Arduino IDE to setup defines, I just added #define EVE_RVT70H in line 157 of EVE_config.h and now it compiles fine without warning for the pre-configured UNO.

Building https://github.com/RudolphRiedel/FT800-FT813/tree/5.x/examples/EVE_Test_Arduino_PlatformIO for Arduino with PlatformIO currently gives this result:

Environment                Status    Duration
-------------------------  --------  ------------
uno                        SUCCESS   00:00:01.478
avr_pro                    SUCCESS   00:00:01.245
nano328                    SUCCESS   00:00:01.271
mega2560                   SUCCESS   00:00:01.267
adafruit_metro_m4          SUCCESS   00:00:07.909
samd21_m0-mini             SUCCESS   00:00:03.296
ESP32                      SUCCESS   00:00:06.676
ESP8266_d1_mini            SUCCESS   00:00:07.362
nucleo_f446re              SUCCESS   00:00:09.247
teensy41                   SUCCESS   00:00:04.204
adafruit_feather_nrf52840  SUCCESS   00:00:05.150
bbcmicrobit_v2             SUCCESS   00:00:02.142
teensy35                   SUCCESS   00:00:02.853
xmc1100_xmc2go             SUCCESS   00:00:04.159
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Spyy

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Re: BT818 PCLK settings
« Reply #29 on: February 03, 2022, 09:43:09 PM »

Hello,

On our development boards we utilize the Abracon LLC - "ABM8G-12.000MHZ-18-D2Y-T" 12Mhz 18pF crystal.

Best Regards,
BRT Community
Hi,

Ok...with this crystal, do i additional external capacitors?

At the moment i am clocking the BT818 chip with an external pwm 50/50 12Mhz signal from my teensy 4.1 and this works fine...but what i saw is that then i get an internal clock of about 69xyz Mhz instead of 72. And when i change my pwm to 12000001 i get 75+Mhz.
Problem was on my custom boards i did not get it to run with an external crystal, it was not starting to clock at all (due to wrong crystal/capacitors???). Only internally worked with a bit confusion results as described...so i changed to external clocking from my teensy...but i want to return to a crystal as recommended..so the value of the capacitors, if needed, would be very interesting..

Thank you

Torsten
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