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Author Topic: BT818 PCLK settings  (Read 3468 times)

durian

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BT818 PCLK settings
« on: September 23, 2021, 09:32:38 PM »

I've got a BT818 on a board of mine and I'm seeing some weird things with respect to the PCLK timing.

1)
The REG_PCLK_FREQ register values don't agree with the datasheet when set by CMD_PCLKFREQ. For example, if I request a frequency of 36 MHz, REG_PCLK_FREQ gets set to 0x461. If you were to interpret that according to the data sheet, you'd get a frequency of 36 MHz, but the range (found in bits 10:9) are 10. That implies a range of 80 - 160 MHz. If we repeat the exercise, but with a frequency of 72 MHz, REG_PCLK_FREQ is 0x8c1 which has a range of 00 which is 20 - 40 MHz.

I think the real range bits are found in bits 11:10, not 10:9. But even then, the range for 36 MHz would be 01, which is 40 - 80 MHz. 36 MHz is below that. Similarly, a clock of 72 MHz gives a range value of 10, which is 80 - 160 MHz. 72 MHz is also below that range.

I'm not sure what's going on here, but the datasheet does not seem to agree with the results from CMD_PCLKFREQ.

2)
When I put a scope on the PCLK output, pin 39, I see a clock that is about half what was programmed. Does data get clocked out on both rising and falling edges? And if so, is that standard? I'm running the output of the BT818 into a TFP410 to create an HDMI signal and I think that chip expects only one pixel per clock cycle, not two. Can anyone explain to me what's going on here?

Thanks,
mike
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Re: BT818 PCLK settings
« Reply #1 on: September 30, 2021, 04:58:04 PM »

Hello,

We will test this and see what results we obtain and then let you know.

Could you please provide an example of the command you are sending and the return values from the command you receive?

To clarify, what are you passing in for ftarget and rounding and what you get back for factual in cmd_pclkfreq( uint32_t ftarget, int32_t rounding, uint32_t factual );

Best regards

BRT Community
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durian

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Re: BT818 PCLK settings
« Reply #2 on: September 30, 2021, 09:45:36 PM »

Here's an example:
cmd = 0xffffff6a
ftarget = 0x030047b0 (50350000)
rounding = 0x00000000
result = 0x02faf080 (50000000)
REG_PCLK_FREQ = 0xd93 (bits 11:9 = b110, bits 8:4 = 25, bits 3:0 = 3)

I need to point out that when I designed this board, I was under the impression that I could use the internal clock on the FT818. Either I was looking at the first version of the datasheet that explicitly allows for this or the revised one where it isn't clear (not listed in the 4.2 System Clock section, but allowed for in 4.9.4 Reset and Boot-up Sequence and mentioned as a feature of the chip on the first page of the datasheet). Now I'm stuck with using the internal clock since BT818's are back-ordered and not currently available.

Perhaps this explains why I need to specify a clock frequency twice as large as I really want.

I don't know if it is related, but I'm not getting any output from R[0] - R[7]. It is specifically those pins, not the color red. It I swizzle a red / blue swap, blue is not output instead of red.

mike
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Re: BT818 PCLK settings
« Reply #3 on: October 01, 2021, 05:03:28 PM »

Hello Mike,

I have passed on this information to an R&D engineer. I will let you know what they think is causing this issue.

Best regards

BRT Community
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Rudolph

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Re: BT818 PCLK settings
« Reply #4 on: October 01, 2021, 05:15:31 PM »

We already had this discussion, sort of:
http://www.brtcommunity.com/index.php?topic=272.msg1336#msg1336

My take on this is that something went wrong with the onchip oscillator with the BT817/BT818 so it has been removed from the specification.
« Last Edit: October 03, 2021, 06:35:31 PM by Rudolph »
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durian

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Re: BT818 PCLK settings
« Reply #5 on: October 05, 2021, 11:24:11 PM »

The on-chip oscillator's accuracy isn't very good, but it's good enough that I can render at 640x480 if I request double the normal PCLK value. At this point, my bigger concern is the lack of output on the R[0..7] pins. Not being able to display red is rather annoying. I am interested to see what the R&D engineer has to say. I'd really like to get things usable enough that I can develop on my board since it might be a while before the chip supply recovers and I can build a new version.

I don't know if there have been multiple updates to the BT818, but REG_DATESTAMP reports "2019-10-28 2.5.3" on mine.

mike
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Re: BT818 PCLK settings
« Reply #6 on: October 06, 2021, 12:08:46 PM »

Hello,

We are still in discussion with the R&D engineer regarding the oscillator/datasheet and will provide a response soon.

On your issue with the display, could you please tell me what display settings you have used for the display registers? The registers are as follows:

#define EVE_DISP_WIDTH 1024 // Active width of LCD display
#define EVE_DISP_HEIGHT 600 // Active height of LCD display
#define EVE_DISP_HCYCLE 1344 // Total number of clocks per line
#define EVE_DISP_HOFFSET 160 // Start of active line
#define EVE_DISP_HSYNC0 0 // Start of horizontal sync pulse
#define EVE_DISP_HSYNC1 100 // End of horizontal sync pulse
#define EVE_DISP_VCYCLE 635 // Total number of lines per screen
#define EVE_DISP_VOFFSET 23 // Start of active screen
#define EVE_DISP_VSYNC0 0 // Start of vertical sync pulse
#define EVE_DISP_VSYNC1 10 // End of vertical sync pulse
#define EVE_DISP_PCLK 1 // Pixel Clock
#define EVE_DISP_SWIZZLE 0 // Define RGB output pins
#define EVE_DISP_PCLKPOL 1 // Define active edge of PCLK
#define EVE_DISP_CSPREAD 0
#define EVE_DISP_DITHER 1

Best regards

BRT Community
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durian

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Re: BT818 PCLK settings
« Reply #7 on: October 06, 2021, 05:55:07 PM »

Here are the relevant register values (plus a couple extra). Also the requested value I passed to CMD_PCLKFREQ and the factual value it selected.

These are values I read from the registers themselves. The timings are for 640x480 @60Hz, though I had to double the requested frequency to get this.

DATESTAMP: 2019-10-28 2.5.3
requested = 50350000
factual = 50000000
FREQUENCY=72000000
PCLK_POL=0x00000001
PCLK=0x00000001
PCLK_2X=0x00000000
PCLK_FREQ=0x00000d93
pclk freq = 50000000
HCYCLE=800
HSIZE=640
HOFFSET=160
HSYNC0=16
HSYNC1=112
VCYCLE=525
VSIZE=480
VOFFSET=45
VSYNC0=10
VSYNC1=12
SWIZZLE=1
CSPREAD=1
DITHER=1
OUTBITS=0
GPIOX=0000108f
GPIOX_DIR=00008000
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durian

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Re: BT818 PCLK settings
« Reply #8 on: October 06, 2021, 10:38:20 PM »

I should probably mention another weird thing, in case it is relevant. I only use single mode SPI, not dual or quad. The fastest I can run the SPI clock is 8 MHz. If I try 9 MHz or faster, I get garbled responses from the BT818.

mike
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Re: BT818 PCLK settings
« Reply #9 on: October 07, 2021, 05:13:15 PM »

Hello,

A general rule for determining the offset values is to use: HOFFSET < (HCYCLE – HSIZE) and VOFFSET < (VCYCLE – VSIZE).

Additionally, you could try changing CSPREAD from 1 to 0.

Hopefully these adjustments will fix your colour issue.

Best regards

BRT Community
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durian

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Re: BT818 PCLK settings
« Reply #10 on: October 07, 2021, 05:58:44 PM »

I'm looking at table 4-14 (page 26) of the datasheet and it says HSIZE is the visible part of the line, HOFFSET is the non-visible part and HCYCLE is the total length of the visible and non-visible parts. To me that would imply that HCYCLE = HSIZE + HOFFSET, or

HOFFSET = HCYCLE - HSIZE

not

HOFFSET < HCYCLE - HSIZE

My timings agree with the first equation and they come from the VESA Display Monitor Timing Standard (DMT) document.

But that said, your suggestion to disable CSPREAD worked! If I turn it off, instead of using the default enabled value, I get all the colors, including red.

Despite the other quirks, the chip is now working well enough that I can make some demos.

One more quirk I should mention. CMD_TESTCARD does not work for me. It just erases the screen. I can see that it adds commands to the display list, but I only get a blank screen. Anything I'd had in the display list before calling CMD_TESTCARD is not displayed either.

Thank you for your help,
mike
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BRT Community

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Re: BT818 PCLK settings
« Reply #11 on: October 08, 2021, 08:57:20 AM »

Hi,

Glad to hear it helped,

Yes, for EVE, you should set your display registers such that:

HOFFSET < (HCYCLE – HSIZE)
VOFFSET < (VCYCLE – VSIZE)

Without this, there can be cases where the swap wont succeed.

Instead of using the CMD_PCLK_FREQ we recommend to set the REG_PCLK_FREQ manually using the table 4-11 in the BT817 datasheet as these are the recommended values for each different PCLK frequency. We will be adding more guidance on this in the datasheet very soon,

Could you advise what your overall command list was to display the test card was?

Best Regards, BRT Community
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durian

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Re: BT818 PCLK settings
« Reply #12 on: October 08, 2021, 07:22:33 PM »

If I compare the REG_PCLK_FREQ values in table 4-11 to the value set by calling CMD_PCLK_FREQ, I see they are the same. I tested all the values in the table and CMD_PCLK_FREQ gives the same REG_PCLK_FREQ value as shown in the table. So CMD_PCLK_FREQ appears to be behaving correctly if the table is also correct. However, both the table and CMD_PCLK_FREQ conflict with the definition for REG_PCLK_FREQ[10:9] listed immediately above table 4-11. Which is correct: CMD_PCLK_FREQ and table 4-11 or the description of bits REG_PCLK_FREQ[10:9].

Regarding the HOFFSET < (HCYCLE - HSIZE) requirement, what is the recommended procedure when you are retrieving timings from the display over DDC? For example, I have a display that reports a preferred timing of:
    74.25 MHz pixel clock
    1280 active horizontal
    370 total horizontal blanking period
    110 horizontal front porch
    40 horizontal sync
    720 active vertical
    30 total vertical blanking period
    5 vertical front porch
    5 vertical sync

The total number of pixels per frame is (1280 + 370) * (720 + 30) = 1237500
74.25 MHz / 1237500 = 60 frames per second

Looking only at the horizontal part,
    HSIZE = 1280
    HOFFSET = 370
    HSYNC0 = 110
    HSYNC1 = 150

To make HOFFSET < (HCYCLE - HSIZE), I'd have to make
    HCYCLE > 1650 [1280 + 370]
but if I did that, then the timing value of 74.25MHz wouldn't be correct.

This above is just one example, but all the standard VESA timings work the same way. They assume (hactive + hblank) * (vactive + vblank) * framerate = pixel clock. There's no room for extra pixel clock cycles.

What's the preferred way to manipulate the supplied timing values to meet the HOFFSET < (HCYCLE - HSIZE) constraint? Reduce the front porch to 0? Maybe make both front and back porch 0 thus reducing HOFFSET to just the sync duration?

As for the test card, I'm doing:
CMD_DLSTART
CMD_TESTCARD
CMD(DISPLAY())
CMD_SWAP

mike
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durian

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Re: BT818 PCLK settings
« Reply #13 on: October 08, 2021, 07:58:04 PM »

I made a mistake when I looked at the REG_PCLK_FREQ[10:9] range bits. I applied the PCLK frequency to the range conditions instead of the PLL2 frequency. When I correctly use PLL2, things start to make more sense.

Table 4-11 and CMD_PCLK_FREQ still agree with each other and almost match the range conditions above the table. The only difference is table 4-11 and CMD_PCLK_FREQ set the range in bits REG_PCLK_FREQ[11:10] instead of REG_PCLK_FREQ[10:9].

So now it is just a matter of determining which is correct. Is the range set in bits 11:10 or in bits 10:9? If it is set in bits 11:10, what happens with bit 9?

mike
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BRT Community

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Re: BT818 PCLK settings
« Reply #14 on: October 12, 2021, 09:51:56 AM »

Hi,

Sorry, we have checked and there is an error in the datasheet, please find the corrections in red below.

The PCLK frequency in EXTSYNC mode can be calculated as:
PLL2 frequency = 12MHz * REG_PCLK_FREQ[9:4]
PCLK frequency = PLL2 frequency / REG_PCLK_FREQ[3:0] / 2
REG_PCLK_FREQ[11:10] is determined by PLL2 frequency range:
00: 20 – 40 MHz
01: 40 – 80 MHz
10: 80 – 160 MHz
11: 160 – 228 MHz

Note that the max PLL2 frequency is 228MHz and so the bits which set this must not be set such that the frequency exceeds this limit.

We are updating the datasheet to
- recommend using the values from the table written to the register instead of using the command to ensure that the values are calculated within limits (these should cover most cases and so can be used directly)
- and to correct this calculation.

Sorry for any inconvenience caused and we will have the document updated as soon as possible,

Best Regards, BRT Community
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