I've got a BT818 on a board of mine and I'm seeing some weird things with respect to the PCLK timing.
1)
The REG_PCLK_FREQ register values don't agree with the datasheet when set by CMD_PCLKFREQ. For example, if I request a frequency of 36 MHz, REG_PCLK_FREQ gets set to 0x461. If you were to interpret that according to the data sheet, you'd get a frequency of 36 MHz, but the range (found in bits 10:9) are 10. That implies a range of 80 - 160 MHz. If we repeat the exercise, but with a frequency of 72 MHz, REG_PCLK_FREQ is 0x8c1 which has a range of 00 which is 20 - 40 MHz.
I think the real range bits are found in bits 11:10, not 10:9. But even then, the range for 36 MHz would be 01, which is 40 - 80 MHz. 36 MHz is below that. Similarly, a clock of 72 MHz gives a range value of 10, which is 80 - 160 MHz. 72 MHz is also below that range.
I'm not sure what's going on here, but the datasheet does not seem to agree with the results from CMD_PCLKFREQ.
2)
When I put a scope on the PCLK output, pin 39, I see a clock that is about half what was programmed. Does data get clocked out on both rising and falling edges? And if so, is that standard? I'm running the output of the BT818 into a TFP410 to create an HDMI signal and I think that chip expects only one pixel per clock cycle, not two. Can anyone explain to me what's going on here?
Thanks,
mike