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[Cyrilou]

Hi,

I'm experiencing some glitches on my screen of my device sometimes.

Could you help me to set REG values for display initialization with attached files?

      PIXVOFFSET = ?
      PIXHOFFSET = ?
      HCYCLE = ?
      HOFFSET = ?
      HSYNC0 = ?
      HSYNC1 = ?
      VCYCLE = ?
      VOFFSET = ?
      VSYNC0 = ?
      VSYNC1 = ?
      PCLK = ?
      SWIZZLE = ?
      PCLK_POL = ?
      HSIZE = 480;   //ok
      VSIZE = 272;   //ok
      CSPREAD = ?
      DITHER = ?

System clock is 72MHz.

Thanks.

[Rudolph]

That looks like a panel similar to what is used in the RVT43H or the PS817-043WQ-C-IPS.

#define EVE_HSIZE (480L)
#define EVE_VSIZE (272L)
#define EVE_VSYNC0 (0L)
#define EVE_VSYNC1 (4L)
#define EVE_VOFFSET (12L)
#define EVE_VCYCLE (292L)
#define EVE_HSYNC0 (0L)
#define EVE_HSYNC1 (4L)
#define EVE_HOFFSET (43L)
#define EVE_HCYCLE (531L)
#define EVE_PCLK (7L)
#define EVE_PCLKPOL (1L)
#define EVE_SWIZZLE (0L)
#define EVE_CSPREAD (0L)

[Cyrilou]

Thanks for your reply.

But if my system clock is 72MHz PCLK=8? or both work?

[Rudolph]

But if my system clock is 72MHz PCLK=8? or both work?

With 72MHz system clock and PLCK=7 you get 10.286MHz pixel-clock and 66.34Hz,
with PCLK=8 it is 9MHz and 58.05Hz.
So yes, PCLK=7 is for 72MHz system clock and yes, both settings should be fine.

And of course, if you are using a BT817 you could use the second PLL and set it to 9.333MHz pixel clock for 60.19Hz.
Plus you can modify the timing parameters a little for fine-tuning, these are not strictly fixed, it should not hurt for example to make HCYCLE a bit larger.