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Author Topic: BRT AN 033 BT81X Series Programming Guide  (Read 8591 times)

Rudolph

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BRT AN 033 BT81X Series Programming Guide
« on: March 31, 2020, 07:50:43 PM »

I noticed that version 1.2 has been released and when I checked the revision history I "only" lists clarifications for CMD_ANIMFRAME.
When I compared that to version 1.1 I found that the new document has fewer pages as well.
So I sent it thru a diff tool.

Some reformating, minor fixes, excellent.
The offset for REG_SPI_WIDTH is still wrong though.


Then I found this in chapter 2.4 on page 15:
3. Send Host command “ACTIVE” and wait for at least 300 milliseconds. Ensure that there is
no SPI access during this time.
4. Read REG_ID till it is 0x7C

This is from the version 1.1:
3. Send Host command “ACTIVE” and wait for at least 300 milliseconds.
4. Read REG_ID till it is 0x7C

And for comparision, this is from the FT81x guide 1.2:
2. Send Host command “ACTIVE” to enable the clock to the FT81X. FT81X starts its selfdiagnosis process and may take up to 300ms.
 Alternatively, read REG_ID repeatedly until 0x7C is read.

Why has this changed to a fixed 300ms and why was this made stricter now and forbids SPI access during this time?

I am using this for years now:
Code: [Select]
while(chipid != 0x7C) /* if chipid is not 0x7c, continue to read it until it is, EVE needs a moment for it's power on self-test and configuration */
{
DELAY_MS(1);
chipid = EVE_memRead8(REG_ID);
timeout++;
if(timeout > 400)
{
return 0;
}
}

And i works just fine with BT81x as well, I only increased the timeout to 400ms.

But for this post I went a step ahead and measured how long a couple of displays actually need:

EVE2-35G: 69
EVE3-35G: 42
EVE3-35G initialised as EVE2-35G: 75
EVE3-43G: 42
EVE3-43G initialised as EVE2-43G: 69
RiFT43: 42
EVE2-50G: 77
EVE3-50G: 42
EVE3-50G initialised as EVE2-50G: 72

No, these are not all my displays but the pattern is obvious.
FT81x need less than 80ms.
BT815 need less than 45ms since I set their clock to 72MHz.
And when I use a BT815 like a FT813 the startup delay becomes very similar.

Is there any compelling reason why I still should switch to a fixed delay of 300ms with no SPI access?
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BRT Community

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Re: BRT AN 033 BT81X Series Programming Guide
« Reply #1 on: April 01, 2020, 03:01:09 PM »

Hello,

Thanks for your question and your insight, I will have to defer to the development team on the part concerning the 300ms delay. But I believe that the stipulation concerning SPI access is to prevent the unintentional writing or overwriting of registers during the start up process.

Best Regards,
BRT Community
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Rudolph

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Re: BRT AN 033 BT81X Series Programming Guide
« Reply #2 on: April 01, 2020, 06:34:18 PM »

Okay, read-only would be back to the FT81x documentation.  :)

I saw this before and just hooked up my Logik Analyzer again to verify it,
EVE does not respond at all on the SPI during reset.

BT815_startup_01.png : just zoomed out from the end of the Power-Down Delay to the first couple of responses
BT815_startup_02.png : zoom-in on the first access with CLKEXT, CLKSEL and ACTIVE
BT815_startup_03.png : zoom-in on the SPI traffic before the first response
BT815_startup_04.png : zoom-in on the first two responses.
The first answer from EVE is the 0x7c my code is waiting for.
After that my code starts to read REG_CPURESET and the answer is 0x02 which means that the touch-controller is not done resetting.

Looks a bit like it EVE is locked but then at least host commands CLKEXT, CLKSEL and ACTIVE are working.

This makes me wonder what happens if I send EVE more host commands right after ACTIVE. :)
But then, it works now, no need to break it on purpose. :)
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Re: BRT AN 033 BT81X Series Programming Guide
« Reply #3 on: April 08, 2020, 05:03:44 PM »

Hello,

The 300ms delay on start-up is considered as a safety timer to guarantee the chip internal boot-up sequence has completed.

Best Regards,
BRT Community
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Rudolph

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Re: BRT AN 033 BT81X Series Programming Guide
« Reply #4 on: April 08, 2020, 06:05:24 PM »

But what is the reason for the escalation?

We went from:

Code: [Select]
1. Send Host command “CLKEXT” to FT81X, if an external clock is used.
2. Send Host command “ACTIVE” to enable the clock to the FT81X. FT81X starts its selfdiagnosis process and may take up to 300ms. Alternatively, read REG_ID repeatedly until
0x7C is read.
3. Configure video timing registers, except REG_PCLK

to

Code: [Select]
1. Send host command “CLKEXT” if the PLL input is from external crystal oscillator or external
clock.
2. Send host command “CLKSEL” to select system clock frequency if the non-default system
clock is to be used.
By default the system clock is set to 60MHz. However, 72MHz is recommended for better performance.
3. Send Host command “ACTIVE” and wait for at least 300 milliseconds.
4. Read REG_ID till it is 0x7C
5. Read REG_CPUREST till EVE goes into the working status.
6. Configure display control timing registers, except REG_PCLK

and now

Code: [Select]
1. Send host command “CLKEXT” if the PLL input is from external crystal oscillator or external
clock.
2. Send host command “CLKSEL” to select system clock frequency if the non-default system
clock is to be used.
By default the system clock is set to 60MHz. However, 72MHz is recommended for better performance.
3. Send Host command “ACTIVE” and wait for at least 300 milliseconds. Ensure that there is
no SPI access during this time.
4. Read REG_ID till it is 0x7C
5. Read REG_CPUREST till EVE goes into the working status.
6. Configure display control timing registers, except REG_PCLK

To repeat my question:
Why has this changed to a fixed 300ms?
And why was this made stricter now and forbids SPI access during this time?

I am doing this now and it works just fine:

Code: [Select]
0. drive PD_N low, wait 6ms, drive PD_N high, wait 21 ms
1. Send Host command “CLKEXT” to FT81X, if an external clock is used.
2. If we have a BT81x: Send host command “CLKSEL”
3. Send Host command “ACTIVE” to enable the clock
4. Read REG_ID till it is 0x7C or exit if 400ms have passed
5. Read REG_CPUREST till EVE goes into the working status or exit if 50ms have passed
6. Tell BT81x that it runs at 72MHz
7. Reconfigure or patch the touch-controller if necessary
8. disable the backlight
9. Configure video timing registers, except REG_PCLK

I could throw in a delay_ms(40) between 3 and 4 to leave EVE alone for a moment, based on my above measurements.
But 300ms does really not seem to be necessary, it even is excessive for the FT81x.
And I never had an issue with reading REG_ID directly after ACTIVE.

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